International Business Machines Corporation

Amir Turi

Giora Biran

Eyal Naor

Erez Barak

Yossi Shapira

Yair Fried

Osher Yifrach

Avraham Ayzenfeld

Yanai Danan

Gilad Merran

Amit Shay

Oren Ben Gigi

Omri Rafaeli

In an approach to processor dependency-aware instruction execution, responsive to a new instruction being issued to an instruction issue queue in a processor, a future dependency count is incremented for each instruction of a plurality of instructions in the instruction issue queue that has a dependency on the new instruction. The plurality of instructions in the instruction issue queue are prioritized based on the future dependency count. The highest priority instruction of the plurality of instructions in the instruction issue queue is issued.

Processor dependency-aware instruction execution

Prefetching data by detecting a predefined pattern of register activity of a computer processor by detecting when data, at a memory address pointed to by the sum of an offset value and the contents of a register of the processor during an instruction cycle of the processor, is loaded into the register as a result of processing an instruction, detecting the pattern by detecting when data, at a memory address pointed to by the sum of the offset value and the contents of the register during at least one subsequent instruction cycle, is loaded into the register as a result of again processing the instruction, and prefetching data, into a cache memory of the processor, from a current prefetching memory address, where data, at a memory address pointed to by the sum of the offset value and the contents of the register, is used as the current prefetching memory address.

Prefetching data based on register-activity patterns

A move data instruction to move data from one location to another location is obtained. Based on obtaining the move data instruction, a determination is made as to whether the data to be moved is located in a buffer. The buffer is configured to maintain the data for use by multiple move data instructions. The buffer is used to move the data from the one location to the other location, based on determining that the data to be moved is in the buffer.

Reducing latency of common source data movement instructions

Examples of techniques for executing instructions out of order are described herein. An example computer-implemented method includes receiving, via a processor, a plurality of instructions to be executed. The method includes sending, via the processor, an instruction to a minimal dependency queue in response to detecting the instruction includes a minimally dependent instruction. The method also includes selecting, via the processor, an instruction from a set of instructions that are eligible to be executed based on a scheme. The method further includes executing, via the processor, the instruction.

Executing processor instructions using minimal dependency queue

The present disclosure provides reducing clock power consumption of a computer processor by simulating, in a baseline simulation of a computer processor design using a software model of the computer processor design, performance of an instruction by the computer processor design, to produce a baseline result of the instruction, and identifying a circuit of the computer processor design that receives a clock signal during performance of the instruction, and in a comparison simulation of the computer processor design using the software model of the computer processor design, simulating performance of the instruction by the computer processor design while injecting a corruption signal into the circuit, to produce a comparison result of the instruction, and designating the circuit for clock gating when processing the instruction, if the comparison result of the instruction is identical to the baseline result of the instruction.

Reducing clock power consumption of a computer processor

Reducing clock power consumption of a computer processor by simulating, in a baseline simulation of a computer processor design using a software model of the computer processor design, performance of an instruction by the computer processor design, to produce a baseline result of the instruction, and identifying a circuit of the computer processor design that receives a clock signal during performance of the instruction, and in a comparison simulation of the computer processor design using the software model of the computer processor design, simulating performance of the instruction by the computer processor design while injecting a corruption signal into the circuit, to produce a comparison result of the instruction, and designating the circuit for clock gating when processing the instruction, if the comparison result of the instruction is identical to the baseline result of the instruction.

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Ramat Gan, Israel

Amir Turi