Mellanox Technologies, Ltd.

Mellanox Technologies Tlv Ltd.

Amir Rosen

Gil Levy

Sagi Lahav

Arye Albahari

Shie Mannor

Ariel Szapiro

Tsofia Eshel

Elad Alon

In one embodiment, a system includes prefetcher engines to predict next memory access addresses of a memory from which to load data to a cache during execution of a software application, and load the data from the predicted next memory access addresses to the cache during execution of the software application, and a processor to control the prefetcher engines according to configurations of the prefetcher engines selected by a machine learning agent in exploration phases and in exploitation phases during execution of the software application, and execute the machine learning agent to select from a pruned set of configurations to control the prefetcher engines in the exploration phases, perform measurements on the system during execution of the machine learning agent, and execute the machine learning agent to select from the configurations to maximize potential rewards from controlling the prefetcher engines in the exploitation phases based on the performed measurements.

Prefetcher engine configuration selection with multi-armed bandit

In one embodiment, a system includes prefetcher engines to predict next memory access addresses of a memory from which to load data to a cache during execution of a software application, and load the data from the predicted next memory access addresses to the cache during execution of the software application, and a processor to assign cache replacement precedence values to cache lines based on the prefetcher engines that loaded the cache lines, and evict the cache lines from the cache based on the cache replacement precedence values of the cache lines.

Cache replacement system

In one embodiment, a system includes a processor to reduce a number of cache replacement precedence value policies available for selection by a machine learning agent, each cache replacement precedence value policy including an array of predefined cache replacement precedence values for corresponding different combinations of (a) prefetcher engines that loaded cache lines, and (b) event-types of events that have been performed on the cache lines, and a memory to store data used by the processor.

Reducing set of policies with two or more hyper-dimensions

An apparatus includes multiple processors, a classifier and queue management logic. The classifier is configured to classify tasks, which are received for execution by the processors, into multiple processor queues, each processor queue associated with a single processor or thread, and configured to temporarily store task entries that represent the tasks, and to send the tasks for execution by the associated processors. The queue management logic is configured to set, based on queue-lengths of the queues, an affinity strictness measure that quantifies a strictness with which the tasks of a same classified queue are to be processed by a same processor, and to assign the task entries to the queues while complying with the affinity strictness measure.

Multi-processor queuing model

In a packet network of ingress nodes and egress nodes connected by a fabric transmit queues are associated with a hash table that stores packet descriptors. When new packets are received in the ingress nodes, credits are obtained from the egress nodes that reflect capacities of the transmit queues to accommodate the new packets. The credits are consumed by transmitting at least a portion of the new packets from the ingress nodes to the egress nodes via the fabric and storing descriptors of the new packets in a hash table. In order to transmit the packets in order by sequence number, when a desired packet sequence number is found by a hash lookup, the new packet having that sequence number is forwarded through the egress nodes.

Growing community of inventors

Haifa, Israel

Amir Rosen