International Business Machines Corporation

Samsung Electronics Co., Ltd.

Amazon Technologies, Inc.

Apple Inc.

Technion Research & Development Foundation Limited

Amir Nahir

Vitali Sokhin

Wisam Kadry

James Nicholas Klazynski

Allon Adir

Ara Cho

Sung-Boem Park

Jin Sung Park

Shimon Landa

Gil Eliezer Shurek

Jeffrey Norbert Coonen

Alex Umansky

Lee Abe Teichner

Ran Yad Shalom

Orel Shai

Sofia Gendelman

Ophir Friedler

Dimtry Krestyashyn

Jue Wang

Shakti Kapoor

Manoj Dusanapudi

Oded Margalit

John Andrew Schumann

Yehuda Naveh

Anatoly Koyfman

Behjat Siddiquie

Shady Copty

Eyal Bin

Charles Meissner

Dan Raz

Elena Tsanko

Ilia Averbouch

Yossi Shiloach

Ariel Orda

Randal S Thelen

Yair Dagan

Hadi Khader

Yuval Gonczarowski

Shany Mordehai

Melissa Cheng

Maxim Golubev

Andrey Klinger

This disclosure describes, in part, techniques for retrieving images based on detecting events. For instance, system(s) may detect an event, such as an event associated with a collection of images for an item. Based on detecting the event, the system(s) may determine an area within a facility, such as an inventory location, for retrieving image data. The system(s) may then determine one or more imaging devices that have field(s) of view of the area. Additionally, the system(s) may score the imaging device(s) based on visibility data associated with the imaging device(s). The system(s) may also determine occlusion data for image data generated by the imaging device(s). Using the scores and the occlusion data, the system(s) may then select image data that represents the area. The system(s) may then store the image data in one or more data stores, such as with the collection of images.

Techniques for generating collection of images

Techniques for obtaining images of items

A method, apparatus and computer program product to be employed by a hardware component under validation, wherein the hardware component having a plurality of processing units each belonging to one of at least two types, such that one of the at least two types of processing units is less error-prone then a remainder of the at least two types. The method comprising: designating one of the processing units of the hardware component under validation that belongs to the less error-prone type as a manager processing unit; initiating execution of a tester program code for testing processing units, by processing units of the hardware component other than the manager processing unit; and, monitoring by the manager processing unit the status of the processing units during execution of the tester program code.

Validation of multiprocessor hardware component

A method, apparatus and computer program product to be employed by a hardware component under validation, wherein the hardware component having a plurality of processing units each belonging to one of at least two types, such that one of the at least two types of processing units is less error-prone than a remainder of the at least two types. The method comprising: designating one of the processing units of the hardware component under validation that belongs to the less error-prone type as a manager processing unit; initiating execution of a tester program code for testing processing units, by processing units of the hardware component other than the manager processing unit; and, monitoring by the manager processing unit the status of the processing units during execution of the tester program code.

A method comprising, in a cloud computing system: receiving a new job at the cloud computing system; sampling VMs (Virtual Machines) of the cloud computing system for the load currently handled by each of the VMs; if the load currently handled by the VMs is within operational bounds, sending the new job to one of the VMs which currently handles the highest load compared to other ones of the VMs; and if the load currently handled by the VMs is beyond operational bounds, sending the new job to one of the VMs which currently handles the lowest load compared to other ones of the VMs.

Distributed cloud computing elasticity

An approach for improving efficiency of cycle-reproducible debug in a multi-core environment is provided. The approach executes an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds. The approach determines a seed from the one or more different seeds that locates a fail-condition. Responsive to determining a seed from the one or more different seeds that locates the fail condition, the approach determines an upper bound and a lower bound of the fail-condition. The approach determines an exact cycle where the fail-condition occurs. The approach constructs a multi-cycle trace for the fail-condition.

Efficiency of cycle-reproducible debug processes in a multi-core environment

A method includes holding a definition of multiple software-implemented tests for testing one or more hardware units of an Integrated Circuit (IC), and of invocation conditions that specify whether the tests are permitted to run. The tests are applied to the hardware units at least partially in parallel, using a processor in the IC, by repeatedly tracking respective execution states of the tests and evaluating the invocation conditions, and invoking a test that currently does not run but is permitted to run in accordance with the invocation conditions.

Concurrent validation of hardware units

A method, apparatus and product for test generation. The method comprises generating a first set of instructions for a hardware component, that are to be executed when operating in a first mode of operation; in response to a parsed template statement being a marker statement, generating an intermediary set of one or more instructions to cause the hardware component to change the mode of operation to a second mode in accordance with the marker instruction, and modifying the expected mode of the hardware component to a second mode; and generating a second set of instructions for the hardware component, that are to be executed when operating in the second mode of operation. The generation of instructions comprises determining the expected mode and generating instructions in accordance with the expected mode of the hardware component. The generation is performed without having an expected full state of the hardware component.

Test generation using expected mode of the target hardware device

Localizing errors by: (i) running the testcase on a software model version of a processor to yield first testcase-run results in the form of a first set of values respectively stored in the set of data storage locations; (ii) creating a resource dependency information set based on the instructions of the testcase; (iii) running the testcase on a hardware version of the processor to yield second testcase-run results in the form of a second set of values respectively stored in the set of data storage locations; (iv) determining a set of miscompare data storage location(s), including at least a first miscompare data storage location, by comparing the first set of values and the second set of values; and (v) creating an initial dynamic slice of the data flow.

Architectural failure analysis

A method for configuring a Field Programmable Gate Array (FPGA) with a Constraint Satisfaction Problem (CSP) assignment having multiple constraint expressions, the method comprising: setting each of the multiple constraint expressions as a configurable logic block (CLB) in the FPGA, to yield multiple CLBs; setting an assignment vector in the FPGA, wherein the assignment vector is a number vector configured to store a candidate solution to the CSP assignment; and forming a feedback loop by connecting the assignment vector to inputs of the multiple CLBs, and connecting outputs of the multiple CLBs to the assignment vector. Further disclosed is a design structure for the FPGA, optionally residing on a storage medium as a data format used for the exchange of layout data of integrated circuits.

Solving constraint satisfaction problems using a field programmable gate array

Localizing errors by: (i) running a testcase on a hardware processor and saving results; (ii) running the testcase on a software model of the processor and saving results; (iii) recording control flow information during the software run; (iv) determining a set of miscompare data storage locations by comparing the results from the hardware run with those from the software run; (v) based on the set of miscompare data storage locations and/or the control flow information, generating and running a modified version of the testcase that takes a different execution path when run on the software model than did the original testcase when run on the software model; and (vii) comparing the results from the hardware run and the results obtained from the modified software run to provide an indication of similarity between execution paths taken in these respective runs.

Control flow error localization

Method, system and product for post silicon validation using a partial reference model. The method performed by a device having registers, the method comprising: first executing, by the device when operating in trace mode, a test-case, wherein during the execution utilizing a partial reference model to determine an expected value of at least one register; second executing, by the device when operating in non-trace mode, the test-case; and in response to said second executing, checking values of registers based on, at least in part, values determined during said first execution.

Post-silicon validation using a partial reference model

Growing community of inventors

Megadim, Israel

Amir Nahir