Intel Corporation

Amir Leibovitz

Ido Ouziel

Robert Valentine

Zeev Sperber

Stephan Jourdan

Ittai Anati

Ron Gabor

James G Hermerding, Ii

Lihu Rappoport

Franck Sala

Bob Valentine

Gregory Pribush

Sudheer Nair

Leeor Peled

Hanna Alam

Yoav Almog

Avishai Wagner

Refael Mizrahi

Moran Peri

Ido Karavany

Gilad Olswang

Ronen Laperdon

Hadas Beja

Michal Moran

Jonathan Beimel

Disclosed Methods, Apparatus, and articles of manufacture to dynamically enable and/or disable prefetchers are disclosed. An example apparatus include an interface to access telemetry data, the telemetry data corresponding to a counter of a core in a central processing unit, the counter corresponding to a first phase of a workload executed at the central processing unit; a prefetcher state selector to select a prefetcher state for a subsequent phase based on the telemetry data; and the interface to instruct the core in the central processing unit to operate in the subsequent phase according to the prefetcher state.

Methods and apparatus to dynamically enable and/or disable prefetchers

Methods and apparatus for using micro-op caches in processors are disclosed. A tag match for an instruction pointer retrieves a set of micro-op cache line access tuples having matching tags. The set is stored in a match queue. Line access tuples from the match queue are used to access cache lines in a micro-op cache data array to supply a micro-op queue. On a micro-op cache miss, a macroinstruction translation engine (MITE) decodes macroinstructions to supply the micro-op queue. Instruction pointers are stored in a miss queue for fetching macroinstructions from the MITE. The MITE may be disabled to conserve power when the miss queue is empty-likewise for the micro-op cache data array when the match queue is empty. Synchronization flags in the last micro-op from the micro-op cache on a subsequent micro-op cache miss indicate where micro-ops from the MITE merge with micro-ops from the micro-op cache.

Efficient method and apparatus for employing a micro-op cache in a processor

A micro-operation (uop) fusion technique. More particularly, embodiments of the invention relate to a technique to fuse two or more uops originating from two or more instructions.

Representing a plurality of instructions with a fewer number of micro-operations

Growing community of inventors

Biniamina, Israel

Amir Leibovitz