Cadence Design Systems, Inc.

Tellabs San Jose, Inc.

Amir Lehavot

Vinaya Kumar Singh

Axel Siegfried Scherer

Joezac John Zachariah

Jose Barandiaran

Adam Julian Goldstein

Mohammad Kamel Issa

Mark David Griswold

Mitri Halabi

Raghavan Menon

Xiaoyang Zheng

Shaham Parvin

Embodiments of the present invention relate to portions of a switch fabric having a single logical stage and at least one physical stage. In addition, the data paths and the control paths of the switch fabric can be decoupled thereby allowing additional processing to be performed than would otherwise be the case with control rates that matched the high data rates. In other words, data cells received on high speed links can be spread over many lower speed links; consequently, the data cells can transit the switch fabric at that high speed while the control information associated with the data can be processed at that lower speed. Because the control information can be processed at a lower speed (associated with the control path), the control information can be processed over a greater period of time.

Apparatus and method for a fault-tolerant scalable switch fabric with quality-of-service (QOS) support

An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.

Automated debugging method for over-constrained circuit verification environment

Automated debugging method and system for over-constrained circuit verification environment

Method for providing information associated with an over-constrained event in verification of a circuit design

Method for checking a status of a signal port to identify an over-constrained event

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Amir Lehavot