Broadcom Corporation

Avago Technologies International Sales Pte. Limited

Avago Technologies General IP Pte, Ltd.

Amir Hadji-Abdolhamid

Hooman Darabi

Mohyee Mikhemar

Ahmad Mirzaei

Masoud Kahrizi

Janice Chiu

Bernd Pregardier

According to one embodiment, a compact low-power receiver comprises first and second analog circuits connected by a digitally controlled interface circuit. The first analog circuit has a first direct-current (DC) offset and a first common mode voltage at an output, and the second analog circuit has a second DC offset and a second common mode voltage at an input. The digitally controlled interface circuit connects the output to the input, and is configured to match the first and second DC offsets and to match the first and second common mode voltages. In one embodiment, the first analog circuit is a variable gain control transimpedance amplifier (TIA) implemented using a current mode buffer, the second analog circuit is a second-order adjustable low-pass filter, whereby a three-pole adjustable low-pass filter in the compact low-power receiver is effectively produced.

Adjustable low-pass filter in a compact low-power receiver

A single hybrid receiver is provided for processing both single carrier and carrier aggregated (CA) communications signals where carriers are split into independent receive paths without any additional external components. The receiver receives all contiguous and non-contiguous intra-band CA and inter-band CA signals, including those of unequal bandwidths, allowing for improved rejection and balanced rejection of jamming signals on either side of the two carrier signals.

Receiver for carrier aggregation

A single hybrid receiver is provided for processing both single carrier and carrier aggregated (CA) communications signals where carriers are split into independent receive paths without any additional external components. The receiver receives all contiguous and non-contiguous intra-band CA and inter-band CA signals allowing for improved rejection and balanced rejection of jamming signals on either side of the two carrier signals.

An envelope detector (ED) includes a voltage-mode ED core including parallel detection transistors for detecting a voltage envelope of an RF signal input. The detection transistors are configured with a size and for a current such that the transistors are biased in subthreshold regions of operation. The ED core is configured to variably control a bias current through the detection transistors, where the bias current is varied according to a voltage amplitude of the RF signal input to enhance a linear range of the ED while detection transistors continue to operate in subthreshold regions. A linearizer circuit may be configured to control the bias current based on feedback inputs from ED outputs. Several gain-programmable voltage amplifiers, which may include a final specialized class-AB amplifier, precede the ED core, to adapt a transmitter output voltage to an input range of the ED core, which extends the linear range of the ED.

Envelope detector with enhanced linear range

A circuit for a low-noise interface between an amplifier and an analog-to-digital converter (ADC) may comprise a capacitor element having a capacitance of C coupled between a first and second output node of the amplifier. A resistor circuit coupled between the capacitor element and input nodes of the ADC. A desired value Rfor a load resistance of the amplifier is provided by selecting suitable initial values for resistances of the resistor circuit. A desired bandwidth for the at least one amplifier is achieved by selecting a value of the capacitance C based on the desired value Rfor the load resistance.

TIA-to-ADC interface with low-noise and a wide-range of passive gain control

Receiver with variable gain control transimpedance amplifier

Device including a plurality of analog circuits and an interface that matches characteristics of the analog circuits

A circuit for a low-noise interface between an amplifier and an analog-to-digital converter (ADC) may comprise a capacitor element having a capacitance of C coupled between a first and second output node of the amplifier. A first resistor Rmay be coupled in parallel with the capacitor. A second resistor Rmay be coupled between the first output node of the amplifier and a first input node of the ADC. A third resistor Rmay be coupled between the second output node of the amplifier and a second input node of the ADC. Initial values of the resistances R, R, and Rmay be selected to provide a desired value Rfor a load resistance of the amplifier. A value of the capacitance C may be selected so that, in combination with the desired value R, a desired bandwidth for the amplifier is achieved.

Low-noise TIA-to-ADC interface with a wide-range of passive gain control

An envelope detector (ED) includes a voltage-mode ED core including parallel detection transistors for detecting a voltage envelope of a radio frequency (RF) signal input, the RF signal input including an output of a radio such as a cellular transmitter (TX). The ED further includes multiple voltage amplifiers positioned serially in gain stages between the TX output and the ED core to provide a total linear voltage range of the envelope detector. A final voltage amplifier of the multiple voltage amplifiers drives the ED core and includes a class-AB RF amplifier configured to operate within a full linear voltage range of the ED core.

Class-AB radio frequency amplifier for envelope detector

According to one embodiment, a high performance buffer for use in a communications system includes first and second differential blocks. Each of the first and second differential blocks comprise one or more driving transistors for generating a driving current for a load of the high performance buffer, and a feedback path for adjusting the operation of the one or more driving transistors. The feedback path includes a feedback transistor for receiving a common mode bias voltage, wherein the common mode bias voltage depends at least in part on a threshold voltage of the feedback transistor. The feedback path includes a programmable resistor and capacitor to reduce out of band loop gain and the noise. The high performance buffer is configured to achieve a high linearity, low output impedance, and low noise, and is suitable for use as a pre-mixer buffer in a wireless communications system.

High performance pre-mixer buffer in wireless communications systems

According to one embodiment, an improved preamplification chain for implementation in a transmitter comprises a frequency conversion stage for up-converting a baseband signal to a transmit signal, a variable gain control power amplifier driver for preamplifying the transmit signal, and a differential feedback calibration stage receiving first and second differential outputs of a current steering unit of the power amplifier driver and providing calibration feedback to a baseband signal generator of the transmitter. In one embodiment, the frequency conversion stage includes an adjustable low-pass filter for filtering the baseband signal, a passive mixer for up-converting the baseband signal to the transmit signal, and a clock conversion unit configured to convert a fifty percent (50%) duty cycle clock input to a twenty-five percent (25%) duty cycle clock output for driving the passive mixer.

High performance transmitter preamplification chain with calibration feedback

Compact low-power receiver including transimpedance amplifier, digitally controlled interface circuit, and low pass filter

Embodiments of a capacitive tuning system implementing a tunable capacitive array are presented herein. The tunable capacitive array includes both scaled coarse capacitors and one or more fine capacitors. The one or more fine capacitors advantageously reduce a differential nonlinearity associated with the scaled coarse capacitors. The use of fine capacitors limits additional area requirements in an integrated circuit implementation, while improving the accuracy of the capacitive tuning system.

System and method for reduced area tunable capacitors

An integrated circuit includes a signal-path filter, a high-pass filter, and a control circuit. The signal-path filter is configured to receive an input signal and provide an output signal. The high-pass filter is coupled to the signal-path filter and is configured to reduce a direct-current (DC) component of the input signal. The high-pass filter includes a metal-oxide-semiconductor (MOS) switch, wherein a corner frequency of the high-pass filter is based on a resistance of the MOS switch. The control circuit is configured to provide a control voltage to the MOS switch. The control circuit includes a reference resistor, wherein the resistance of the MOS switch substantially tracks the resistance of the reference resistor. The integrated circuit may be embodied in software and/or included in a device (e.g., a mobile telephone) that receives and filters a signal.

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Aliso Viejo, CA, United States of America

Amir Hadji-Abdolhamid