Marvell Israel (misl) Ltd.

Marvell Semiconductor Israel Ltd.

Amir Gabai

David Moshe

Shmuel Dino

Tomer Labin

Aron Wohlgemuth

Amit Avivi

Aspects of the disclosure provide a CAM module that can be used independent of a defective entry line. The CAM module can include at least a CAM array having at least X CAM entry lines, and an additional CAM entry line. Each CAM entry line may include a selection line for enabling the CAM entry line for writing and/or reading and an entry output for indicating matching to a search key. Further, the CAM module can include a decoder unit that can decode an address to enable one out of X word-lines, and an encoder unit that can encode X matching outputs to a matching address according to a predetermined priority sequence. Additionally, the CAM module can include a switching unit coupling the CAM array with the decoder unit and the encoder unit. The switching unit can select X CAM entry lines from the X+1 CAM entry lines based on a defective status of the CAM array; correspond the X word-lines of the decoder unit to the selection lines of the selected X CAM entry lines; and correspond the entry outputs of the selected X CAM entry lines to the X matching outputs of the encoder unit.

Method and apparatus for CAM with redundancy

A method of delaying an input signal comprises serially receiving the input signal at a plurality of rows of delay elements; applying a row selection signal to a row of delay elements to select the row from the plurality of rows; supplying a column selection signal to a tap buffer associated with a delay element in the selected row to select an output of the delay element; coupling outputs of tap buffers associated with delay elements in each row to form an output of each row; coupling outputs of each of the plurality of rows to provide an incrementally-delayed input signal from the selected row; outputting the incrementally-delayed input signal from the selected delay element in the selected row; and changing row selection from the selected row to a contiguous row of the plurality of rows in the absence of a change in the selection of the corresponding tap buffers.

Diagonal matrix delay

A circuit having a corresponding method comprises one or more circuits each to produce one or more status signals, wherein each of the status signals represents a status of a respective one of the one or more circuits; a memory; a memory controller to store a plurality of samples of the one or more status signals in the memory; a plurality of input/output terminals; an interface in communication with one or more of the input/output terminals; and a debug circuit to transfer the one or more samples of the status signals from the memory to the interface.

Integrated circuit with integrated debugging mechanism for standard interface

A diagonal matrix delay includes a plurality of rows of first buffers in serial communication with an input signal. The diagonal matrix delay includes a plurality of second buffers. Each second buffer is responsive to an output of an associated first buffer and to a column selection signal. The diagonal matrix delay includes a plurality of control lines. Each control line supplies column selection signals to the corresponding second buffers associated with each of the plurality of rows. Corresponding second buffers controlled by a control line are offset between contiguous rows by at least one column to form a substantially diagonal arrangement of columns of second buffers relative to the plurality of rows of first buffers.

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Modiin, Israel

Amir Gabai