Rambus Inc.

Samsung Display Co., Ltd.

Leland Stanford Junior University

Samsung Electronics Co., Ltd.

Amir Amirkhany

Mohammad Hekmat

Dinesh D Patil

Kambiz Kaviani

Frederick Abbott Ware

Suresh Rajan

Aliazam Abbasfar

Vladimir Marko Stojanovic

Gaurav Malhotra

Anup P Jose

Jared L Zerbe

Ravindranath T Kollipara

Farrukh Aquil

Ian P Shaeffer

David A Secker

Chaofeng Huang

Brian S Leibowitz

Mohamed N Elzeftawi

Younghoon Song

Mark A Horowitz

Huy M Nguyen

John M Wilson

Lei Luo

Elad Alon

Sanquan Song

Michael D Bucher

Hsuan-Jung (Bruce) Su

Farshid Aryanfar

Jalil Kamali

Nasrin Jaffari

Wendemagegnehu Beyene

Valentin Abramzon

Jason Chia-Jen Wei

Kyunglok Kim

Ranick Ng

Bruno Werner Garlepp

Carl William Werner

Kun-Yung Chang

Wei Xiong

Reza Navid

Wayne D Dettloff

Ralf M Schmitt

Moonsang Hwang

Hajee Mohammed Shuaeb Fazeel

Minghui Han

Ali Fazli Yeknami

Da Wei

Michael Wang

Gundlapalli Shanmukha Srinivas

Amr Khashaba

Michael Chung Wang

Neal Hays

Sam Ray

Xingchao (Chuck) Yuan

Charlene Ku

T Gary Yip

Ashkan Roshan Zamir

Sabarish Sankaranarayanan

Kim Kyunglok

A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

Semiconductor memory systems with on-die data buffering

A system and method of clock and data recovery. In some embodiments, the method includes: setting a bias signal source to a first bias value, the bias signal source being connected to an input of a voltage-controlled oscillator of a clock and data recovery circuit; determining that a locked signal of a frequency feedback signal source equals a first feedback value; setting the bias signal source to a second bias value, different from the first bias value; determining that a locked signal of the frequency feedback signal source equals a second feedback value; determining that the second feedback value meets a termination criterion; and setting an operating value of the bias signal source to the second bias value.

System and method of clock and data recovery

Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

Optimizing power in a memory device

A system includes a first encoder configured to receive first input bits and generate a first stream of first bits based on the first input bits, a bit generator configured to receive second inputs bits and generate a second stream of second bits based on the second input bits, and a PAM4 transmitter configured to receive the first stream of first bits and the second stream of second bits, and generate PAM4 symbols based at least on the first stream of first bits.

Systems and methods for transition encoding compatible PAM4 encoding

A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

Folded memory modules

A method for encoding may include receiving, at an encoder, a series of data bits, performing, at the encoder, first transition encoding on the data bits to generate an encoded series of data bits based on a key, performing, at the encoder, protection encoding on the key to generate key protection data, performing, at the encoder, second transition encoding on the key protection data to generate encoded key protection data, and transmitting an encoded series of transmission bits to a receiver, the encoded series of transmission bits including the encoded series of data bits and the encoded key protection data.

Systems and methods for decoding transition encoded data with protected key

A method for compensating for transistor aging in a display device is presented. The method entails dividing pixels into a plurality of groups including a first group, the first group including Z pixels wherein Z>1, sampling a pixel current for each pixel in a subset of pixels in the first group, the subset including M pixels wherein 1≤M≤Z, determining an Errorusing the sampled pixel current for the M pixels and a predefined reference current, and adjusting an input voltage for a transistor in more than one of the Z pixels based on the Error. The adjusting of the input voltage may include generating a modified voltage V, whereinand each of A and B is determined using Σsign(Error).

Multi-pixel collective adjustment for steady state tracking of parameters

A clock recovery circuit may include: a data slicer configured to output data values based on an input signal, a first error block, a phase adjustment loop including: a first error slicer configured to generate a first error signal based on a comparison of a threshold voltage and an input voltage, wherein the first error block is configured to selectively output the first error signal in response to a first pattern in the output data values, a second error block configured to selectively output the first error signal in response to a second pattern in the output data values, and a voltage threshold modification circuitry configured to adjust the threshold voltage based on output of the second error block, a voltage-controlled oscillator, wherein the data slicer and the first error slicer are clocked based on output of the voltage-controlled oscillator.

Systems and methods for symbol-spaced pattern-adaptable dual loop clock recovery for high speed serial links

A receiver for a serial data link, including an analog front end (AFE) including a continuous-time linear equalizer (CTLE) configured to receive an input signal from a transmitter, the CTLE including a first output node; a second output node; a plurality of programmable tail current sources configured to adjust a direct current (DC) offset between the first output node and the second output node; and a calibration circuit including: a slicer configured to output a difference between a first average output voltage corresponding to the first output node and a second average output, voltage corresponding to the second output node; and a calibration counter configured to increment or decrement an offset count based on the difference, wherein the plurality of programmable tail current sources are adjusted based on a value of the offset count.

Real-time DC-balance aware AFE offset cancellation

Systems and methods for transition encoding with protected key

A method of encoding input data includes dividing the input data into a plurality of data packets, an input packet of the plurality of data packets including a plurality of digits in a first base system, base-converting the input packet from the first base system to generate a base-converted packet including a plurality of converted digits in a second base system, the second base system having a base value lower than that of the first base system, and incrementing the converted digits to generate a coded packet for transmission through a communication channel.

Near-optimal transition encoding codes

A method of compensating for change in pixel and a display device incorporating such method are presented. The method includes dividing pixels into groups including a previous group L&#x2212;1, a current group L and a next group L+1; determining A[L] and B[L] for each pixel in the current group L; for each pixel in the current group L, determining a first moving average A[L] and a second moving average B[L] as follows: wherein A[L&#x2212;1] is a first moving average of a pixel in the corresponding column in the previous group L&#x2212;1, B[L&#x2212;1] is a second moving average of a pixel in the corresponding column in the previous group L&#x2212;1, and K is a moving average window; and for the next group L+1, setting a first initial value A[L+1] and a second initial value A[L+1] of each pixel to A[L] and B[L].

Fast external pixel compensation in a display panel

Growing community of inventors

Sunnyvale, CA, United States of America

Amir Amirkhany