Smart Modular Technologies, Inc.

Hgst Technologies Santa Ana, Inc.

Amir Alavi

Dillip Kumar Dash

Lun Bin Huang

Jinying Shen

Umang Thakkar

Rajesh Ananthanarayanan

An memory management system with backup system, and a method of operation of a memory management system with backup system thereof, including: a memory module controller for detecting a power failure condition, the memory module controller including a nonvolatile memory controller; a compression controller integrated within the nonvolatile memory controller for receiving a data block from volatile memory; a compression engine within the compression controller for compressing the data block to form a compressed data block; and a sequencer for writing the compressed data block to nonvolatile memory.

Memory management system with backup system and method of operation thereof

Approaches, techniques, and mechanisms are disclosed for improving the performance of memory controllers for memory devices. A system may have a memory controller that interfaces with a memory device to store or retrieve information. When the system needs to retrieve information from the memory device, the memory controller sends an address and a command to instruct the memory device to read the information stored at the address. The memory device reads the information, and after a specific amount of time, the memory device sends the information to the memory controller. According to an embodiment, 'dummy' data is sent first prior to the availability of the data read out of the memory devices, while waiting for the requested data to be accessed, and then the actual data is sent immediately following the dummy data. According to an embodiment, a geometry of a memory device has only one column of memory cells that are used to store information. The memory device with only one column in an embodiment does not require decoding of a column address. As such, the read latency of the memory device is significantly reduced.

Memory controller for high latency memory devices

Aspects of the subject disclosure relate to a storage device including a flash memory, a controller coupled to the flash memory, wherein the controller is configured to store data to the flash memory and a power arbiter unit coupled to the controller and to the flash memory via a plurality of flash channels, wherein the power arbiter unit is configured to receive a plurality of power requests via one or more of the plurality of flash channels and process the plurality of power requests based on a respective priority identifier associated with each of the plurality of power requests. Additionally, a computer-implemented method and power arbiter unit (PAB) are provided.

Growing community of inventors

Irvine, CA, United States of America

Amir Alavi