Cadence Design Systems, Inc.

Ambrish Kant Varma

Kumar Chidhambara Keshavan

Xuegang Zeng

Kenneth Robert Willis

Bradford Griffin

Taranjit Singh Kukal

Hui Qi

Feras Al-Hawari

Rameet Pal

Ping Liu

Jilin Tan

Dennis Nagle

Zhongyong Zhou

Jose Emmanuel Schutt-Aine

Qi Zhao

Delong Cai

Shivani Sharma

Shangli Wu

Yubao Meng

Disclosed are methods and systems for characterizing and analyzing an electronic system design including a parallel interface. Some methods and systems identify an electronic design including a parallel interface, determine a single circuit representation including the parallel interface from the electronic design, and analyze the parallel interface to determine waveform responses of the parallel interface by using channel analysis techniques without performing circuit simulations. Some other methods and systems are directed at performing channel analyses for a communication interface of an electronic system by concurrently applying stimuli to corresponding transmitters of a communication interface, characterizing the communication interface to perform a single simulation on the communication interface with the stimulus to determine responses at receivers of the communication interface, and determining waveform responses of the communication interface by performing operations on the responses and an input signal to the communication interface.

Method, system, and computer program product for performing channel analyses for an electronic circuit design including a parallel interface

Embodiments included herein may be used for characterizing and analyzing an electronic system design including a parallel interface. Embodiments may include identifying an electronic design including a design of a parallel interface. Embodiments may also include determining a single circuit representation including the design of the parallel interface from the electronic design. Embodiments may further include analyzing the single circuit representation at a channel analysis module stored at least partially in memory and functioning in tandem with a computing system to determine waveform responses of the parallel interface and a remainder of the single circuit representation by using channel analysis techniques. The channel analysis techniques may be based upon a data channel simulation and a strobe channel simulation. Embodiments may also include generating or modifying the electronic design including the design of the parallel interface based in part or in whole upon results of analyzing the single circuit representation.

System and method for simulating channels using true strobe timing

The present disclosure relates to a system and method for algorithmic modeling interface ('AMI') model development. Embodiments may include enabling a selection from a plurality of templates associated with an advanced equalization algorithm at a graphical user interface. Embodiments may further include receiving a selection of at least one of the plurality of templates at the graphical user interface and displaying a selected template at the graphical user interface. Embodiments may also include allowing a user to edit one or more parameters associated with the selected template at the graphical user interface and generating an algorithmic modeling interface ('AMI') model based upon, at least in part, the selected template and the one or more parameters.

Algorithmic modeling interface process

The present disclosure relates to non-linear systems associated with an electronic circuit design. Embodiments may include identifying the non-linear system associated with the electronic circuit design and determining a degree of severity of non-linearity of the non-linear system associated with the electronic circuit design. If the degree of severity is less than a predefined threshold, embodiments may further include receiving a random input pattern and deriving a single impulse response characterization, wherein the random input pattern is based upon, at least in part, an electronic circuit simulation associated with the electronic circuit design.

System and method for enhanced characterization for system identification of non-linear systems

The present disclosure relates to a system and method for use with an electronic circuit design. The method may include providing, using at least one processor, an electronic design and modeling the electronic design to obtain a characteristic distribution associated with the electronic design, wherein modeling includes randomly varying one or more parameters associated with the electronic design. The method may further include identifying at least one key parameter from the modeled electronic design and reducing the electronic design only to the at least one key parameter. The method may also include in response to reducing, randomly varying the one or more parameters and re-modeling the reduced electronic design with the randomly varied one or more parameters.

System and method for electronic design space tuning

The present disclosure relates to a system and method for simulating channels in an electronic circuit design. Embodiments may include receiving, at one or more computing devices, an electronic circuit design including at least one channel. Embodiments may further include transmitting two or more inputs from two or more transmitter drivers on two or more wires to the at least one channel. In some embodiments, the inputs may be distributed across the wires based upon a chordal code. Embodiments may also include generating simulated waveforms based upon the inputs. Embodiments may further include transmitting the simulated waveforms from the channel on the wires to a comparator block. Embodiments may also include comparing the simulated waveforms on the wires at the comparator block to produce two or more simulated outputs. Embodiments may include transmitting the simulated outputs from the comparator block on the wires to two or more post-comparator receivers.

System and method for simulating channels

The present disclosure relates to a computer-implemented method for transient simulation of an input/output buffer model. The method may include generating an input/output buffer data file associated with a first model of an electrical circuit. The method may also include determining at least one of a node voltage and a branch current associated with the electrical circuit using, at least in part, a latency insertion method, the method may further include performing one or more simulations on a second model of an electrical circuit, the one or more simulations incorporating, at least in part, the input/output buffer data file and the latency insertion method.

System, method, and computer program product for input/output buffer modeling

A method and systems are provided for screening and rapid evaluation of routed nets in a post-layout circuit environment, such as in the design of printed circuit boards. A portion of nets are selected for determination of associated signal quality factors. Signal channels containing one or more selected nets are then built. A reference input stimulus is propagated along each of the signal channels in a frequency based simulation for generating characteristic responses of the selected nets' signal channels. A signal channel quality factor is obtained for each signal channel based upon its characteristic response. The signal channels and their nets are then comparatively analyzed according to corresponding signal channel quality factors to selectively identify any aberrant nets warranting supplemental evaluation for faults.

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Chelmsford, MA, United States of America

Ambrish Kant Varma