Freescale Semiconductor,inc.

Globalfoundries Inc.

Freescale Semiconductors Inc.

Le Centre National De La Recherche Scientifique (cnrs)

Nxp Usa, Inc.

Amaury Gendron

Chai Ean Gill

Rouying Zhan

Andy C Wei

Patrice Besse

Philippe Renaud

Changsoo Hong

Vadim A Kushner

Jagar Singh

Jin Ping Liu

Shao Ming Koh

Nicolas Nolhier

Gopal Srinivasan

Devices and methods for forming semiconductor devices with wider FinFETs for higher tunability of the varactor are provided. One method includes, for instance: obtaining an intermediate semiconductor device; applying a spacer layer over the semiconductor device; etching the semiconductor device to remove at least a portion of the spacer layer to expose the plurality of mandrels; removing the mandrels; etching the semiconductor device to remove a portion of the dielectric layer; forming at least one fin; and removing the spacer layer and the dielectric layer. One intermediate semiconductor device includes, for instance: a substrate; a dielectric layer over the substrate; a plurality of mandrels formed on the dielectric layer, the mandrels including a first set of mandrels and a second set of mandrels, wherein the first set of mandrels have a width twice as large as the second set of mandrels; and a spacer layer applied over the mandrels.

Devices and methods of forming higher tunability FinFET varactor

Integrated circuits with relaxed silicon and germanium fins and methods for fabricating such integrated circuits are provided. The method includes a forming a crystalline silicon and germanium composite layer overlying a crystalline silicon substrate, where a composite layer crystal lattice is relaxed. A fin is formed in the composite layer, and a gate is formed overlying the fin. A portion of the fin is removed on opposite sides of the gate to form a drain cavity and a source cavity, and a source and a drain are formed in the source cavity and drain cavity, respectively.

Integrated circuits with relaxed silicon / germanium fins

An electrostatic discharge (ESD) protection clamp () for protecting associated devices or circuits (), comprises a bipolar transistors () in which doping of facing base () and collector () regions is arranged so that avalanche breakdown occurs preferentially within a portion () of the base region () of the device () away from the overlying dielectric-semiconductor interface (). Maximum variations (&#x394;Vt)of ESD triggering voltage Vtas a function of base-collector spacing dimensions D due, for example, to different azimuthal orientations of transistors () on a semiconductor die or wafer is much reduced. Triggering voltage consistency and manufacturing yield are improved.

ESD protection device and method

Methods for forming an electrostatic discharge protection (ESD) clamps are provided. In one embodiment, the method includes forming at least one transistor having a first well region of a first conductivity type extending into a substrate. At least one transistor is formed having another well region of a second opposite conductivity type, which extends into the substrate to partially form a collector. The lateral edges of the transistor well regions are separated by a distance D, which at least partially determines a threshold voltage Vtof the ESD clamp. A base contact of the first conductivity type is formed in the first well region and separated from an emitter of the second conductivity type by a lateral distance Lbe. The first doping density and the lateral distance Lbe are selected to provide a parasitic base-emitter resistance Rbe in the range of 1&#x3c;Rbe&#x3c;800 Ohms.

Methods for forming electrostatic discharge protection clamps with increased current capabilities

An area-efficient, high voltage, single polarity ESD protection device () is provided which includes an p-type substrate (); a first p-well (-) formed in the substrate and sized to contain n+ and p+ contact regions () that are connected to a cathode terminal; a second, separate p-well (-) formed in the substrate and sized to contain only a p+ contact region () that is connected to an anode terminal; and an electrically floating n-type isolation structure (-) formed in the substrate to surround and separate the first and second semiconductor regions. When a positive voltage exceeding a triggering voltage level is applied to the cathode and anode terminals, the ESD protection device triggers an inherent thyristor into a snap-back mode to provide a low impedance path through the structure for discharging the ESD current.

Area-efficient high voltage bipolar-based ESD protection targeting narrow design windows

An ESD protection device, which is arranged to be active at a triggering voltage (Vt) for providing ESD protection, comprises a first region of the first conductivity type formed in a semiconductor layer of the first conductivity type, the first region extending from a surface of the semiconductor layer and being coupled to a first current electrode (C) of the semiconductor device, a well region of a second conductivity type formed in the semiconductor layer extending from the surface of the semiconductor layer, and a second region of the second conductivity type formed in the well region, the second region being coupled to a second current electrode (B). The ESD protection device further comprises a floating region of the second conductivity type formed in the semiconductor layer between the first current electrode (C) and the well region and extending from the surface of the semiconductor layer a predetermined depth. The floating region is separated from the well region by a predetermined distance, a value of which is selected such that the floating region is located within a depletion region of a PN junction between the well region and the semiconductor layer when the ESD protection device is active. The floating region has a doping concentration selected such that the floating region is not fully depleted when the ESD protection device is active and the predetermined depth is selected such that the floating region modifies a space charge region near the PN junction. An ESD protection device according to a second embodiment is also disclosed.

ESD protection device and method of forming an ESD protection device

Methods are provided for producing stacked electrostatic discharge (ESD) clamps. In one embodiment, the method includes providing a semiconductor substrate in which first and second serially-coupled transistors are formed. The first transistor includes a first well region having a first lateral edge partially forming the first transistor's base. The second transistor including a second well region having a second lateral edge partially forming the second transistor's base. Third and fourth well regions are formed in the first and second transistors, respectively, and extend a different distance into the substrate than do the well regions of the first and second transistors. The third well region has a third lateral edge separated from the first lateral edge by a first spacing dimension D. The fourth well region has a fourth lateral edge separated from the second lateral edge by a second spacing dimension D, which is different than D

Methods for producing stacked electrostatic discharge clamps

Embodiments include methods for forming an electrostatic discharge (ESD) protection device coupled across input-output (I/O) and common terminals of a core circuit, where the ESD protection device includes first and second merged bipolar transistors. A base of the first transistor serves as collector of the second transistor and the base of the second transistor serves as collector of the first transistor, the bases having, respectively, first and second widths. A first resistance is coupled between an emitter and base of the first transistor and a second resistance is coupled between an emitter and base of the second transistor. ESD trigger voltage Vtand holding voltage Vh can be independently optimized by choosing appropriate base widths and resistances. By increasing Vh to approximately equal Vt, the ESD protection is more robust, especially for applications with narrow design windows, for example, with operating voltage close to the degradation voltage.

Methods of forming voltage limiting devices

A stackable electrostatic discharge (ESD) protection clamp () for protecting a circuit core () comprises, a bipolar transistor () having a base region () with a base contact () therein and an emitter () spaced a lateral distance Lbe from the base contact (), and a collector () proximate the base region (). The base region () comprises a first portion () including the base contact () and emitter (), and a second portion () with a lateral boundary () separated from the collector () by a breakdown region () whose width D controls the clamp trigger voltage, the second portion () lying between the first portion () and the boundary (). The damage-onset threshold current Itof the ESD clamp () is improved by increasing the parasitic resistance Rbe of the emitter-base region (), by for example, increasing Lbe or decreasing the relative doping density of the first portion () or a combination thereof.

ESD protection with increased current capability

A stacked electrostatic discharge (ESD) protection clamp (-) for protecting associated devices or circuits () comprises two or more series coupled (stacked) bipolar transistors () whose individual trigger voltages Vtdepend on their base-collector spacing D. A first (--) of the transistors () has a spacing Dchosen within a D range Zwhose slope (&#x394;Vt/&#x394;D) has a first value (&#x394;Vt/&#x394;D), and a second (--) of the transistors () has a spacing value Dchosen within a D range Zor Zwhose slope (&#x394;Vt/&#x394;D) has a second value (&#x394;Vt/&#x394;D)less than the first value (&#x394;Vt/&#x394;D). The sensitivity of the ESD stack trigger voltage Vtto base-collector spacing variations &#x394;D during manufacture is much reduced, for example, by as much as 50% for a 2-stack and more for 3-stacks and beyond. A wide range of Vtvalues can be obtained that are less sensitive to unavoidable manufacturing spacing variations &#x394;D.

Stacked ESD protection

An electrostatic discharge (ESD) protection device coupled across input-output (I/O) and common terminals of a core circuit, comprises, first and second merged bipolar transistors. A base of the first transistor serves as collector of the second transistor and the base of the second transistor serves as collector of the first transistor, the bases having, respectively, first width and second width. A first resistance is coupled between an emitter and base of the first transistor and a second resistance is coupled between an emitter and base of the second transistor. ESD trigger voltage Vtl and holding voltage Vh can be independently optimized by choosing appropriate base widths and resistances. By increasing Vh to approximately equal Vtl, the ESD protection is more robust, especially for applications with narrow design windows, for example, with operating voltage close to the degradation voltage.

Voltage limiting devices

A semiconductor device structure comprises a plurality of vertical layers and a plurality of conductive elements wherein the vertical layers and plurality of conductive elements co-operate to function as at least two active devices in parallel. The semiconductor device structure may also comprise a plurality of horizontal conductive elements wherein the structure is arranged to support at least two concurrent current flows, such that a first current flow is across the plurality of vertical conductive elements and a second current flow is across the plurality of horizontal conductive elements.

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Scottsdale, AZ, United States of America

Amaury Gendron