Intel Corporation

Arm Limited

Amarnath Shanmugam

Yew Keong Chong

Gus Wai-Yan Yeung

Feroze Merchant

Jacek Wiatrowski

Steve P Ferrera

Srinivas Rajamani

Anik Basu

Described is an apparatus which comprises: a pass-gate; a sleep transistor configured as a diode-connected device controllable by the pass-gate; and a word-line driver coupled to the sleep transistor and the pass-gate.

Apparatus for improving read stability

An integrated circuit memoryincorporates a first array of bit cellsand a second array of bit cellswith word line driver circuitrydisposed therebetween. Word line helper circuitryis disposed at the opposite edges of the arrayto the word line driver circuitry. The helper circuitry is responsive to the word line signal on a word linebeing driven towards an asserted value to switch on and further drive the word line signal towards the asserted value. The helper circuitry is switched off by a global reset signal, which may be a self-timed global reset signal.

Integrated circuit memory with word line driving helper circuits

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Austin, TX, United States of America

Amarnath Shanmugam