Texas Instruments Corporation

Amarjit Singh Bhandal

Keith Balmer

Iain Craig Robertson

John D Keay

Karl M Guttag

David J Hoyle

Richard D Simpson

Sanjive Agarwala

Charles Lance Fuoco

David A Comisky

Zahid Hussain

Graham B Short

Christopher L Mobley

Anthony S Rowell

Robert J Harrison

Christopher J Hall

A transfer request bus and transfer request bus node is described which is suitable for use in a data transfer controller processing multiple concurrent transfer requests despite the attendant collisions which result when conflicting transfer requests occur. Transfer requests are passed from an upstream transfer request node to downstream transfer request node and then to a transfer request controller with queue. At each node a local transfer request can also be inserted to be passed on to the transfer controller queue. Collisions at each transfer request node are resolved using a token passing scheme wherein a transfer request node possessing the token allows a local request to be inserted in preference to the upstream request.

Transfer request bus node for transfer controller with hub and ports

A method for processing data using a multiplexing architecture includes performing a selected one of a plurality of first multiplexer operations on the data and then a selected one of a plurality of second multiplexer operations. The first multiplexer operations include a pass operation and a plurality of bit rearrangement operations. The second multiplexer operations include a pass operation and a plurality of bit duplication operations which duplicates a selected bit or bits to a corresponding block of contiguous bits in the output. A result is then generated that reflects the outputs produced by first and second multiplexers respectively.

System and method for using a two-stage multiplexing architecture for performing combinations of passing, rearranging, and duplicating operations on data

An embodiment of the invention includes a pair of parallel 16&times;16 multipliers each with two 32-bit inputs and one 32-bit output. There are options to allow input halfword and byte selection for four independent 8&times;8 or two independent 16&times;16 multiplications, real and imaginary parts of comple&times;multiplication, pairs of partial sums for 32&times;32 multiplication, and partial sums for 16&times;32 multiplication. There are options to allow internal hardwired routing of each multiplier unit results to achieve partial-sum shifting as required to support above options. There is a redundant digit arithmetic adder before final outputs to support additions for partial sum accumulation, complex multiplication vector accumulation and general accumulation for FIRs/IIRs&mdash;giving MAC unit functionality. There are options controlled using bit fields in a control register passed to the multiplier unit as an operand. There are also options to generate all of the products needed for complex multiplication.

Data processor with flexible multiply unit

Data transfer between a master node ( ) and plural memory nodes ( ) follows a synchronous fixed latency loop bus ( ). Each memory node includes bus interface ( ) which passes command, write data, address and read data to a next memory node in the loop. Each memory node performs a read from its memory at the specified address if a read command is directed to it. Each memory node performs a write to its memory at the specified address if a write command is directed to it. This configuration provides a fixed latency between the issue of a read command and the return of the read data no matter which memory node is accessed. This configuration prevents collision of returning read data. This configuration retains the issued read and write order preserving proper function for read/write and write/read command pairs. This configuration provides fixed loading to each stage regardless of the number of memory nodes. Thus the design of large systems operating at high speeds is simplified.

Method and apparatus for data transfer employing closed loop of memory nodes

A transfer request bus ( ) is described which is suitable for use in a data transfer controller processing, multiple concurrent transfer requests despite the attendant collisions which result when conflicting transfer requests occur. Transfer requests are passed from an upstream transfer request node ( ) to downstream transfer request node ( ) and thence to a transfer request controller with queue ( ). At each node a local transfer request can also be inserted to be passed on to the transfer controller queue. Collisions at each transfer request node are resolved using a token passing scheme wherein a transfer request node possessing the token allows a local request to be inserted in preference to the upstream request.

Distributed service request system for providing fair arbitration using token passing scheme to resolve collisions

A processing device ( ) provides general-purpose input/output pins ( ) for use by software routines as needed. A data input register ( ) has bits corresponding to each pin ( ) for storing the value of the signal on the pin. A data output register ( ) has bits corresponding to each pin for driving the signal on the pin ( ) to a desired value. An output enable register ( ) controls output buffers ( ) coupled between the output register ( ) and the pins ( ). A plurality of mask registers ( ) may be individually set to define a set a pins associated with the mask. Each of the data registers, the data input register ( ), the data output register ( ) and the output enable register ( ) are accessed through a plurality of addresses, where the address specifies both the data register being accessed and an associated mask register ( ). Logic ( ) accesses the data registers in view of the state of the associated mask register ( ).

Input/output system with mask register bit control of memory mapped access to individual input/output pins

The present invention provides for a statistics Cyclic Redundancy Check (CRC) ) wherein the statistics CRC ( ) is representative of the values contained within a statistics RAM ( ). The statistics CRC ( ) is then used to reduce test vectors by allowing the validity of the statistics to be determined by reading this signature instead of reading all the individual statistics. The signature is regenerated for each complete pass of the statistics, and the contents of this register are only updated when the pass is complete.

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Northants, United Kingdom

Amarjit Singh Bhandal