Cirrus Logic Inc.

Cirrus Logic International Semiconductor Limited

Amar Vellanki

John L Melanson

Xiaofan Fei

Johann Guy Gaboriau

Tejasvi Das

Xin Zhao

Wai-Shun Shum

Venugopal Choukinishi

Zhong You

Alan Mark Morton

Lei Zhu

Ku He

Vamsikrishna Parupalli

Leyi Yin

David M Olivenbaum

Gautham Sivasankar

Vikrant Arumugam

Eric Lindemann

Emmanuel A Marchais

Jing Bai

Stewart G Kenly

Kemal S Demirci

Masoud Farshbaf Zinati

Arun Ramani

Jianhao Chen

Jeffrey Skarzynski

Johann G Gaboriau

A system may include a plurality of devices coupled to one another via a shared digital wired communication link, the plurality of devices comprising a first device configured to periodically transmit a synchronization packet onto the shared digital wired communication link to synchronize other of the plurality of devices to a reference clock of the first device, a second device configured to receive the synchronization packet and transmit one or more first data packets onto the shared digital wired communication link in response to the synchronization packet, and a third device configured to receive the synchronization packet and transmit one or more second data packets onto the shared digital wired communication link in response to the synchronization packet and the one or more second data packets.

Multi-chip synchronization in sensor applications

A phase-lock loop (PLL) circuit provides continuous closed-loop operation when switching between operating modes, which may be selection between multiple oscillators, multiple power modes or frequency divider/multipliers of an local clock generator having one or more oscillator circuits, or other changes that may disrupt operation of the PLL. The PLL includes a loop filter having an input coupled to an output of a phase-frequency comparator that compares the output of the oscillator circuit to a reference and a control circuit for storing and restoring the complete state of the loop filter from the storage in response to a change of operating mode, so that a lock time of the phase-lock loop circuit is reduced when selection of one of the at least two selectable different output frequency ranges of the local clock generator is changed.

Dynamic state management of a phase-lock loop (PLL)

An audio processing system reduces perception of audible artifacts due to changes in an element in an audio channel of the audio processing system. The system reproduces an audio input signal and produces an audio output signal with the audio channel. The channel has an adjustable or selectable element that, responsive to a control signal, changes a characteristic of the audio processing channel, which generates a transient in the audio output signal. The systems include a level detector for measuring a signal level of the audio input signal and a controller responsive to an output of the level detector to determine a masking time interval available from the audio output signal due to signal content in the audio input signal. The controller generates the control signal to change the characteristic of the audio processing channel so that at least a portion of the transient occurs in the masking time interval.

Audio processing system signal-level based temporal masking

A multi-path audio amplification system that provides an output drive signal to electromechanical output transducers provides improved undistorted headroom, reduced path switching noise, and/or improved frequency response performance. Multiple signal amplification paths receive an audio input signal and have corresponding multiple output stages that have differing output impedances. A mode selector selects an active one of the multiple signal amplification paths is selected to supply the output drive signal. Outputs of the multiple output stages are coupled to the electromechanical transducer to provide the output drive signal and at least one of the multiple signal amplification paths includes an equalization filter for filtering the audio input signal to compensate for phase or gain differences referenced from the input to the outputs of the multiple output stages due to interaction between the differing output impedances and an impedance of the electromechanical transducer.

Equalization in a multi-path audio amplifier for canceling variations due to multi-path output impedance differences

An amplification system with an output driver stage for providing an output signal to acoustic output transducers such as speakers or haptic output devices removes signal distortion caused by output stage non-linearities by pre-distorting an input signal. The system includes the output driver stage, an input stage for receiving the input signal, and a processing block that receives the input signal and provides an output signal to the output driver stage. The processing block includes a pre-distortion circuit that applies a pre-distortion function to the input signal to generate the output signal if a signal level of the input signal is greater than a threshold amplitude, and if the signal level is less than or equal to the threshold amplitude, generates the output signal from the input signal by bypassing the pre-distortion circuit.

Signal amplitude-selected signal predistortion in an amplifier

A multi-path subsystem may include a first processing path, a second processing path, a mixed signal return path, and a calibration engine configured to: estimate and cancel a direct current (DC) offset of the mixed signal return path, estimate and cancel a DC offset between the first processing path and the second processing path, estimate and cancel a phase difference between the first processing path and a sum of the second processing path and the mixed signal return path, estimate and cancel a return path gain of the mixed signal return path, and track and correct for a gain difference between the first processing path and the second processing path.

Tracking and correcting gain of open-loop driver in a multi-path processing system

A method for calibrating gain in a multi-path subsystem having a first processing path, a second processing path, and a mixed signal return path, may include low-pass filtering an input signal and a mixed signal return path signal generated from the input signal at subsonic frequencies to generate a filtered input signal and a filtered mixed signal return path signal and tracking and correcting for a gain difference between the first processing path and the second processing path based on the filtered input signal and the filtered mixed signal return path signal.

A method may include applying an excitation signal to a capacitor of the capacitive sensor which causes generation of a modulated signal from an input signal indicative of a variance in a capacitance of the capacitor, detecting the modulated signal with a detector to generate a detected modulated signal that has a phase shift relative to the excitation signal, demodulating the detected modulated signal into an in-phase component and a quadrature component using a reference signal, nullifying the quadrature component by setting a phase of the reference signal relative to the excitation signal to compensate for the phase shift, and outputting the in-phase component as an unmodulated output signal representative of the capacitance.

Capacitive sensor including compensation for phase shift

A method of determining a phase misalignment between a first signal generated from a first signal path and a second signal generated from a second signal path may include obtaining multiple samples of the first signal proximate to when the first signal crosses zero wherein the first signal can be approximated as linear; obtaining multiple samples of the second signal proximate to when the second signal crosses zero wherein the first signal can be approximated as linear; based on the multiple samples of the first signal, approximating a first time at which the first signal crosses zero; based on the multiple samples of the second signal, approximating a second time at which the second signal crosses zero; and determining the phase misalignment between the first signal and the second signal based on a difference between the first time and the second time.

Minimizing phase mismatch and offset sensitivity in a dual-path system

A method for measuring a capacitive sensor output may include applying an excitation signal to a capacitor of the capacitive sensor which causes generation of a modulated signal from a baseband signal, wherein the excitation signal is of a carrier frequency which is higher than frequency content of the baseband signal, demodulating the modulated signal to generate an intermediate signal representative of a capacitance of the capacitor wherein the demodulating is based, at least in part, on the excitation signal, converting the intermediate signal into a pulse-density modulated output signal with a pulse-density modulator, and shaping a noise transfer function of the pulse-density modulator to have an approximate zero at the carrier frequency.

Reducing noise in a capacitive sensor with a pulse density modulator

A method may include receiving a stream of serial pulse-density modulation (PDM) data representing a first channel of data synchronized with a rising edge of a clock associated with the serial PDM data and a second channel of data synchronized with a falling edge of the clock, wherein each of the first channel of data and the second channel of data include encoded datagrams wherein each encoded datagram comprises more than one digital bit, detecting an invalid state associated with the stream, and responsive to detecting the invalid state, determining boundaries of each encoded datagram of the stream based on where within the stream the invalid state occurred.

Zero-latency pulse density modulation interface with format detection

A system may include a digital pulse width modulator subsystem, a first path coupled to an output of the digital pulse width modulator subsystem and configured to drive an open-loop driver stage, a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator, a controller to select between the first path and the second path for processing a signal based on one or more characteristics of the signal, and a calibration subsystem configured to calibrate at least one of a first gain of the first path and a second gain of the second path in order that the first gain and the second gain are at least approximately equal at the time of switching selection between the first path and the second path or vice versa, in order to minimize artifacts due to the switching.

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Cedar Park, TX, United States of America

Amar Vellanki