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Amar Pal Singh Rana

Nirmal K Singh

A female crotch enhancing article with cosmetic human female crotch enhancer volume which is positioned within the outer and inner layer of a human female garment's crotch which gives the simulated appearance of exaggerated contours and curves associated with the human female external genitalia without or with the simulated appearance of the exaggerated pudendal cleft associated with the human female external genitalia to provide the human female wearer with subtle understated sexual expression and subtle non-verbal communication.

Female crotch enhancing article

An absorbent article to absorb and contain human female bodily excretions from the genitalia for placement in the inner crotch portion of an undergarment of a human female wearer; and with a separate cosmetic human female crotch enhancer element which is positioned on garment faceable side and gives the simulated appearance of exaggerated contours and curves associated with the human female external genitalia with the simulated appearance of exaggerated pudendal cleft associated with the human female external genitalia and without or with the simulated pubic hair to provide the human female wearer with subtle understated sexual expression and subtle non-verbal communication.

Absorbent article

The present invention implements structures and method for non-delayed clock dynamic logic circuit configurations with output and/or complementary output with reduced glitch and/or mitigating adverse charge-sharing effects for Complementary Oxide Semiconductor (CMOS) and/or mitigating parasitic bipolar action in Strained/Unstrained Silicon-On-Insulator (SOI) circuits, where insulator may be oxide, nitride of Silicon and the like or Sapphire and the like including a method of synthesis.

Reduced glitch dynamic logic circuit and method of synthesis for complementary oxide semiconductor (CMOS) and strained/unstrained silicon-on-insulator (SOI)

The present invention pertains to automated technology dependent transformations for CMOS digital design synthesis resulting in a combination of CMOS interconnected standard-cells from a target CMOS library being mapped and transistor-level representation of the input design specification. The transistor level type and portion to be represented at the transistor level representation is chosen by a user. The transistor sizing and evaluating the combination of said transistor-level representation and standard-cell mapping are performed iteratively to meet delay, size and power constraints for CMOS.

Technology dependent transformations for CMOS in digital design synthesis

The present invention pertains to automated technology dependent transformations for Silicon-On-Insulator (SOI) in the digital design synthesis, the transformations include the steps of receiving input design specification in the form of technology independent specification or interconnected library of standard-cells; performing the technology dependent transformations in the digital design synthesis, resulting in interconnected SOI standard-cells from a SOI target library accounting for floating body effects, including floating body effects affecting delays over long periods of simulation time or testing over long times on fabricated SOI library cells, or SOI transistor level representations, transistor sizing and evaluating the standard-cell mapping and transistor-level representation for all or portion of the input design specification iteratively to meet delay and power constraints for SOI.

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Sunnyvale, CA, United States of America

Amar Pal Singh Rana