International Business Machines Corporation

Globalfoundries Inc.

Amanda L Tessier

Kevin K Chan

Ravikumar Ramachandran

Min Yang

Dae-Gyu Park

Yue Ke

Brian L Tessier

Annie Levesque

Bryant C Colwill

Dureseti Chidambarrao

Shreesh Narasimha

William K Henson

Ricardo Alves Donaton

Yaocheng Liu

Jeanne-Tania Sucharitaves

Michael D Hulvey

Amit Kumar

Paul Chung-Muh Chang

William K Hensen

A gate structure is formed straddling a first portion of a plurality of semiconductor fins that extend upwards from a topmost surface of an insulator layer. A dielectric spacer is formed on sidewalls of the gate structure and straddling a second portion of the plurality of semiconductor fins. Epitaxial semiconductor material portions that include a non-planar bottommost surface and a non-planar topmost surface are grown from at least the exposed sidewalls of each semiconductor fin not including the gate structure or the gate spacer to merge adjacent semiconductor fins. A gap is present beneath epitaxial semiconductor material portions and the topmost surface of the insulator layer. A second epitaxial semiconductor material is formed on the epitaxial semiconductor material portions and thereafter the second epitaxial semiconductor material is converted into a metal semiconductor alloy.

Low resistance and defect free epitaxial semiconductor material for providing merged FinFETs

A method of automated generation of oxide pillar (PX) slot shapes of a PX layer within silicon-on-insulator (SOI) structures that includes generating a placement grid on recess oxide (RX) shapes, creating PX placement markers on the placement grid along a perimeter of the RX shapes, filtering the PX placement markers, generating a PX slot shape corresponding to each filtered PX placement marker on the RX shapes, correcting location errors associated with the generated PX slot shapes, generating PX slot shapes on RX shapes of a predetermined size for which PX slot shapes were not generated, performing a verification operation of the PX slot shapes, and outputting the PX layer including the verified PX slot shapes.

Automated generation of oxide pillar slot shapes in silicon-on-insulator formation technology

Embodiments of the present invention provide a microelectronic structure including a conductive element contacting a bulk semiconductor region of a substrate, the bulk semiconductor region being separated from a semiconductor-on-insulator ('SOI') layer of the substrate by a buried dielectric layer. The microelectronic structure includes a trench isolation region overlying the buried dielectric layer, the trench isolation region sharing an edge with the SOI layer; a conformal layer overlying the trench isolation region, the conformal layer having a top surface and an opening defining a wall extending from the top surface towards the trench isolation region, the top surface including a lip portion adjacent to the wall; a dielectric layer overlying the top surface of the conformal layer; and a conductive element in conductive communication with the bulk semiconductor region, the conductive element consisting essentially of at least one of a semiconductor, a metal, and a conductive compound of a metal, and extending through the dielectric layer, the opening in the conformal layer, the trench isolation region, and the buried dielectric layer, and the conductive element contacting the lip portion.

Method of forming a guard ring or contact to an SOI substrate

A method is provided of forming a conductive via in contact with a bulk semiconductor region of a semiconductor-on-insulator ('SOI') substrate. A first opening is formed in a conformal layer overlying a trench isolation region. The trench isolation region may share an edge with an SOI layer of the substrate. Desirably, a dielectric layer is deposited over a top surface of the conformal layer and the trench isolation region. A second opening can then be formed which extends through the dielectric layer and the first opening in the conformal layer. Desirably, portions of the bulk semiconductor region and the top surface of the conformal layer are exposed within the second opening. The second opening can then be filled with at least one of a metal or a semiconductor to form a conductive element contacting the exposed portions of the bulk semiconductor region and the top surface of the conformal layer.

A semiconductor structure provides lower parasitic capacitance between the gate electrode and contact vias while providing substantially the same level of stress applied by a nitride liner as conventional MOSFETs by reducing the height of the gate electrode and maintaining substantially the same height for the gate spacer. The nitride liner contacts only the outer sidewalls of the gate spacer, while not contacting inner sidewalls, or only a small area of the inner sidewalls of the gate spacer, therefore applying substantially the same level of stress to the channel of the MOSFET as conventional MOSFETs. The volume surrounded by the gate spacer and located above the gate electrode is either filled with a low-k dielectric material or occupied by a cavity having a dielectric constant of substantially 1.0. The reduced height of the gate electrode and the low-k dielectric gate filler or the cavity reduces the parasitic capacitance.

Semiconductor structure for low parasitic gate capacitance

Growing community of inventors

Poughkeepsie, NY, United States of America

Amanda L Tessier