Alcatel USA Sourcing, L.p.

Altera Corporation

Amanda G Noe

Gregory S Lovelace

Michael H Jette

Steven Dale Sensel

Edgar L Read

Stephen A Deschaine

Dennis K Smith

Mark C Cromwell

Becky J Sampson

William A Moffit

David Matthew Smith

A method detects a programmable pattern (e.g., Ethernet comma or SONET A1A2 frame) and simultaneously byte aligns to that pattern. The technique uses a content addressable memory (CAM) programmed (e.g., selected by the user) with a particular pattern to enable detecting of a symbol or symbols, or pattern, of bits in an incoming serial stream. The circuitry deserializes the serial stream and byte aligns parallel data based on output from the CAM and a state machine.

Pattern detect and byte align circuit using CAM

A distributed digital cross-connect system () is provided. The system includes two or more network interface islands () that connect to the telecommunications network. The system () also includes one or more distributed services nodes (). Each distributed services node () connects to two or more of the network interface islands (). The network interface islands () can transmit data to each other through the distributed services node (). An administration system () is also connected to each distributed services node () and each network interface island (). The administration system () transmits matrix configuration and telecommunications channel routing data to the network interface islands () and the distributed services nodes ().

Distributed digital cross-connect system and method

A timing system for distributing a timing signal includes a master timing system that receives a network timing reference. The master timing system generates a master timing signal from the network timing reference. A distributed services node timing system receives the master timing signal and embeds a timing signal into a data transmission frame. A network interface island receives the data transmission frame and retrieves the embedded timing signal therefrom.

Timing system and method for distributing a timing signal

A distributed digital cross-connect system (,) is provided. The system includes two or more network interface islands (,) that connect to the telecommunications network. The system (,) also includes one or more distributed services nodes (,). Each distributed services node (,) connects to two or more of the network interface islands (,). The network interface islands (,) can transmit data to each other through the distributed services node (,). An administration system (,) is also connected to each distributed services node (,) and each network interface island (,). The administration system (,) transmits matrix configuration and telecommunications channel routing data to the network interface islands (,) and the distributed services nodes (,).

A circuitry (10) is provided for automatically retiming a received synchronous data signal to a local clock. The circuitry (10) includes a first flip-flop (20) operable to register at least one synchronous data signal in response to a receive clock signal and to generate at least one data output signal. An OR gate (26) receives a data latch enable signal and a local clock signal. The local clock signal is frequency coherent with the receive clock signal. The OR gate (26) produces an enable signal. A latch (28) is coupled to the OR gate (26) for receiving the enable signal and in cascading arrangement with the first flip-flop (20). The latch (28) latches the data output signal on the falling edge of the local clock signal when the data latch enable signal is low. The latch (28) holds the latched data output signal as long as the local clock signal and the data latch enable signal are low. When either the local clock signal or the data latch enable signal is high, the latch (28) passes the data output signal. A second flip-flop (30), coupled in cascading arrangement with the latch (28), registers the data output signal passed through the latch (28) in response to the local clock signal. The signal output by the second flip-flop (30) is timed to the local clock signal.

Circuitry for retiming a received data signal

A timing system (100) for coordinating the components of a distributed digital cross-connect system (10) is provided. The timing system (100) includes a master timing system (102) that receives a network timing reference (98, 99) and generates a master timing signal. A distributed services node timing system (104, 106) is connected to the master timing system (102) and receives the master timing signal. The distributed services node timing system (104, 106) then embeds a timing signal in a data transmission frame (150). Two or more digital cross-connect timing systems (108) are connected to the distributed services node timing system (104, 106) and receive the data transmission frame (150). The digital cross-connect timing systems (108) retrieve the embedded timing signal from the data transmission frame (150).

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Plano, TX, United States of America

Amanda G Noe