Intel Corporation

Amanda E Schuckman

Qinglei Zhang

Yueli Liu

Rui Zhang

Sri Chaitra Jyotsna Chavali

Siddharth K Alur

Lilia May

Kristof Darmawikarta

Kyu Oh Lee

Robert Alan May

Sri Ranga Sai Boyapati

Yikang Deng

Chong Zhang

Mark S Hlad

Sri Chaitra J Chavali

Zheng Zhou

Srinivas V Pietambaram

Islam A Salama

Mihir K Roy

Rahul Jain

Amruthavalli Pallavi Alur

Sheng C Li

Andrew James Brown

Wei-Lun Kane Jen

Kyu-Oh Lee

Steve S Cho

Sashi S Kandanur

Amruthavalli Palla Alur

Sri Chaitra Chavali

Chi-Mon Chen

Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

Bridge interconnection with layered interconnect structures

Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.

High density organic interconnect structures

Various embodiments disclosed relate to semiconductor device and method of making the same using functional silanes. In various embodiments, the present invention provides a semiconductor device including a silicon die component having a first silica surface. The semiconductor device includes a dielectric layer having a second surface generally facing the first silica surface. The semiconductor device includes an interface defined between the first surface and the second surface. The semiconductor device also includes a silane based adhesion promoter layer disposed within the junction and bonded to at least one of the first silica surface and the dielectric layer second surface.

Semiconductor device including silane based adhesion promoter and method of making

A method that includes electroplating both sides of a core and the through hole of a core with a conductive material to cover both sides of the core with the conductive material and to form a conductive bridge in the through hole, wherein the core has a thickness greater than 200 microns; etching the conductive material that covers both sides of the core to reduce the thickness of the conductive material to about 1 micron; applying a film resist to the core; exposing and developing the resist film to form patterns on the conductive material on both sides of the core; and electroplating additional conductive material on the (i) conductive material on both sides of the core (ii) conductive material within the through hole; and (iii) conductive bridge to fill the through hole with conductive material without any voids and to form conductive patterns on both sides of the core.

Electronic assembly that includes void free holes

Various embodiments of the disclosure are directed to a semiconductor package and a method for fabrication of the semiconductor package. Further, disclosed herein are systems and methods that are directed to using a photoimagable dielectric (PID) layer with substantially similar mechanical properties as that of a mold material. The disclosure can be used, for example, in the context of bumpless laserless embedded substrate structures (BLESS) technology for wafer/panel level redistribution layer (RDL) and/or fan-out packaging applications. The disclosed embodiments may reduce the need for multiple dry resist film (DFR) lamination steps during various processing steps for semiconductor packaging and can also facilitate multiple layer counts due to the availability of thin PID materials.

Systems and methods for semiconductor packages using photoimageable layers

Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment, different metals are variously electroplated to form a microbump which extends through a surface-level dielectric of a substrate to a seed layer including copper. The microbump includes a combination of tin and zinc that mitigates precipitation of residual copper by promoting the formation of miconstituents in the microbump. In another embodiment, the microbump has a mass fraction of zinc, or a mass fraction of tin, that is different in various regions along a height of the microbump.

Tin-zinc microbump structures and method of making same

Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment, different metals are variously electroplated to form a microbump which extends through a surface-level dielectric of a substrate to a seed layer including copper. The microbump includes nickel and tin, wherein the nickel aids in mitigating an absorption of seed layer copper. In another embodiment, the microbump has a mass fraction of tin, or a mass fraction of nickel, that is different in various regions along a height of the microbump.

Copper seed layer and nickel-tin microbump structures

A metal protected fan-out cavity enables assembly of a package-on-package (PoP) integrated circuit while reducing PoP solder spacing and overall z-height. A horizontal fan-out conductor provides a contact between a die contact and a lower package via. A metal protection layer may be used during manufacture to protect the fan-out conductor, such as providing a laser stop during laser skiving. The metal protection layer materials and an etching solution may be selected to allow for subsequent removal via etching while leaving the fan-out conductor intact. The metal protection layer and fan-out conductor materials may also be selected to reduce or eliminate formation of an intermetallic compound (IMC) between the metal protection layer and the fan-out conductor.

Metal protected fan-out cavity

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Scottsdale, AZ, United States of America

Amanda E Schuckman