Arm Limited

Amanda Ashley Scantlin

James Dennis Dodrill

Anil Kumar Baratam

Susan Marie Graham

Various implementations described herein are directed to a sequential logic device having multiple stages. The sequential logic device may include a first stage having first transistors that are arranged to receive a data input signal and a clock signal and provide a first signal and a second signal based on the data input signal and the clock signal. The sequential logic device may include a second stage having second transistors that are arranged to receive the first signal from the first stage and provide an inverted first signal to a gate of a first pass transistor. The first pass transistor may allow the second signal to pass from the first stage to a second pass transistor based on the inverted first signal, and the second pass transistor may allow the second signal to pass from the first pass transistor to ground based on the clock signal.

Sequential logic device with single-phase clock operation

An apparatus for synchronizing an input signal that is asynchronous to a clock signal received by the apparatus. The apparatus comprising selection circuitry configured to select the input signal and to generate a pair of intermediate signals associated with the selected input signal. The apparatus also comprising resolution circuitry configured to provide differential signals based on the pair of intermediate signals and to resolve meta-stability associated with the differential signals. The apparatus also comprising arbiter circuitry configured to determine a dominant value associated with the differential signals and to generate an intermediate output signal based on the determination. The apparatus further comprising latching circuitry configured to generate an output signal based on the intermediate output signal.

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Buda, TX, United States of America

Amanda Ashley Scantlin