Skhynix Inc.

Intel Corporation

Aman Bhatia

Fan Zhang

Naveen Kumar

Chenrong Xiong

Yu Cai

Yi-Min Lin

Haobo Wang

Meysam Asadi

Xuanxuan Lu

Johnson Yen

Lingqi Zeng

Abhiram Prabhakar

Abhiram Prabahkar

Kyoung Lae Cho

June Lee

David J Pignatelli

Soo Jin Kim

Hongwei Duan

HyungSeok Kim

Santhosh K Vanaparthy

Poovaiah Manavattira Palangappa

Wei-Hao Yuan

Seyhan Karakulak

Ravi H Motwani

Zion S Kwok

Chung-Li Wang

Jianqing Chen

Teodor Vlasov

ShiangJyh Steve Chang

HongChich Chou

Santosh Emmadi

Justin Kang

Michael Hsu

Devices, systems and methods for improving performance of a memory device are described. An example method includes obtaining a plurality of samples corresponding to a probability distribution for each of a plurality of cell voltage distributions of the memory device, each of the plurality of cell voltage distributions corresponding to a read voltage, determining, based on the samples obtained for the plurality of cell voltage distributions, a number of first deep neural networks (DNNs), estimating, for each of the first DNNs, one or more parameters of the corresponding probability distribution based on the plurality of samples, training, based on the samples and the corresponding one or more parameters, each of the first DNNs, and training, based on the samples and the one or more parameters from each of the first DNNs, a second DNN to enable generation of an updated read voltage value for retrieving information from the memory device.

Read threshold prediction in memory devices using deep neural networks

A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.

Data storage device

A controller estimates optimal read threshold values for a memory device using deep learning. The memory device includes multiple pages coupled to select word lines in a memory region. The controller performs multiple read operations on a select type of page for each word line using multiple read threshold sets, obtains fail bit count (FBC) information associated with each read operation, and determines an optimal read threshold set for each word line based on the FBC information. When optimal read threshold sets for the select word lines are different each other, the controller predicts a best read threshold set using the optimal read threshold sets.

Read threshold estimation systems and methods using deep learning

A controller optimizes read threshold values for a memory device using domain transformation. The controller determines, for decoded data of each read operation, an asymmetric ratio (AR) and a number of unsatisfied checks (USCs), the AR indicating a ratio of a number of a first binary value to a number of a second binary value in the decoded data. The controller determines a Z-axis such that AR values of threshold sets are arranged in a set order along the Z-axis. The controller determines an optimum read threshold set using coordinate values on the Z-axis, which correspond to a set AR value and a set USC value.

Read threshold optimization systems and methods using domain transformation

A controller determines, for each read operation, a mathematical model by using a) a set function of a read threshold voltage set among the plurality of read threshold voltages and b) a set checksum value; determines a polynomial regression model based on the mathematical model; determines a parameter set by using multiple computations between input and output matrices based on the polynomial regression model; and estimates a next read threshold voltage for a next read operation based on the parameter set. The controller computes mathematical operation algorithms to replace a normal multiplication operation, a normal division operation and a normal multiplication followed by division operation.

Read threshold estimation system using calculations based on polynomial regression

A scheme for non-parametric optimal read threshold estimation of a memory system. The memory system includes a memory device including pages and a controller including a neural network. The controller performs read operations on a selected page using a read threshold set; obtain the read threshold set, a checksum value and an asymmetric ratio of ones count and zeros count which are associated with decoding of the selected page according to each of the read operations; provide the obtained read threshold set, the checksum value and the asymmetric ratio as input information to the neural network; and estimate, by the neural network, an optimal read threshold voltage based on the input information and weights including a combination of multiple matrices and bias vectors.

System and method for non-parametric optimal read threshold estimation using deep neural network

Methods and apparatuses for generating optimized LDPC codes are proposed. One of the methods is a method for generating an optimized LDPC code for an asymmetric transmis&#xac; sion channel. The method includes receiving an initial LDPC code for the asymmetric transmission channel. Further, the method includes performing a density evolution threshold optimization for the initial LDPC code in order to obtain the optimized LDPC code for the asymmetric transmission channel. A uniformly mixed symmetric channel density for the asymmetric transmission channel is used in the density evolution threshold optimization.

Methods and apparatuses for generating optimized LDPC codes

Embodiments provide a scheme for estimating an optimal read threshold voltage using a deep neural network (DNN) with reduced number of processing. A controller receives first and second program voltage (PV) levels associated with read operations on cells. The controller estimates first and second probability distribution parameter sets representing skew normal distributions of the first and second PV levels, respectively. The controller estimates an optimal read threshold voltage based on the first and second probability distribution parameter sets. The optimal read threshold voltage is a read threshold voltage such that first probability density function (PDF) value of the skew normal distribution of the first PV level is the same as the second PDF value of the skew normal distribution of the second PV level.

Read threshold voltage estimation systems and methods for parametric PV-level modeling

Embodiments provide a scheme for estimating an optimal read threshold voltage using a deep neural network (DNN) with a reduced number of processing. A controller includes a combined neural network, which receives first and second cumulative distribution function (CDF) values, each CDF value corresponding to a program voltage (PV) level associated with a read operation on the cells. The combined neural network generates first and second connection vectors based on the first and second CDF values and first weight values, and estimates an optimal read threshold voltage based on the first and second connection vectors and second weight values.

Systems and methods for modeless read threshold voltage estimation

Embodiments provide a scheme for non-parametric PV-level modeling and an optimal read threshold voltage estimation in a memory system. A controller is configured to: generate multiple optimal read threshold voltages corresponding to multiple sets of two cumulative distribution function (CDF) values, respectively; perform read operations on the cells using a plurality of read threshold voltages; generate cumulative mass function (CMF) samples based on the results of the read operations; receive first and second CDF values, selected from among a plurality of CDF values, each CDF value corresponding to each CMF sample; and estimate an optimal read threshold voltage corresponding to the first and second CDF values, among the multiple optimal read threshold voltages.

Systems and methods for non-parametric PV-level modeling and read threshold voltage estimation

Techniques related to improving the error floor performance of a bit flipping (BF) decoder are described. In some examples, error floor performance is improved through determining a set of unreliable check nodes (CNs) and using information about the set of unreliable CNs to compute the flipping energies of variable nodes (VNs). In this manner, the flipping energies can be computed more accurately, thereby lowering the error floor. The set of unreliable CNs can be built through applying various criteria, such as criteria relating to the path length to an unsatisfied CN, the degree of a VN in a path to an unsatisfied CN, and/or checksum value. Path length and VN degree can be applied as selection criteria to determine which CNs qualify as members of the set of unreliable CNs. Checksum value can be applied as a trigger condition for building and/or using the set of unreliable CNs.

Error floor performance of a bit flipping decoder through identifying unreliable check nodes

Embodiments of the present disclosure provide a scheme for decoding over a small subgraph which highly likely includes some errors. A controller is configured to: control the first decoder to decode the data, read from the memory device, using a parity check matrix for the error correction code; extract one or more subgraphs from the entire bipartite graph of the parity check matrix, which is defined by a plurality of variable nodes and a plurality of check nodes when a particular condition satisfied; and control the second decoder to decode the decoding result of the first decoder using a submatrix of the parity check matrix corresponding to the extracted subgraphs.

Decoding systems and methods for local reinforcement

A non-volatile data storage device includes memory cells arranged in a plurality of blocks and a memory controller coupled to the memory cells for controlling operations of the memory cells. The memory controller is configured to determine if a given block is a bad m-bit multi-level block. In an m-bit multi-level block, each memory cell is an m-bit multi-level cell (MLC), m being an integer equal to or greater than 2. Upon determining that the given block is a good m-bit multi-level block, the memory controller assigns the given block to be an m-bit multi-level user block. Upon determining that the given block is a bad m-bit multi-level block, the memory controller determines if the given block is a good n-bit block. In an n-bit block, each memory cell is an n-bit cell, n being an integer less than m. Upon determining that the given block is a good n-bit block, the memory controller assigns the given block to be an n-bit user block or an n-bit write-buffer block.

Wafer-yields and write-QoS in flash-based solid state drives

Devices, systems and methods for improving performance of a memory device are described. An example method includes receiving one or more parameters associated with a plurality of previous read operations on a page of the memory device, wherein the previous read operations are based on a plurality of read voltages, determining, using the one or more parameters as an input to a deep neural network comprising a plurality of layers, an updated plurality of read voltages, wherein each of the plurality of layers is a fully connected layer, and applying the updated plurality of read voltages to the memory device to retrieve information from the memory device, wherein the deep neural network uses a plurality of weights that have been processed using at least one of (a) a pruning operation, (b) a non-uniform quantization operation, or (c) a Huffman encoding operation.

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San Jose, CA, United States of America

Aman Bhatia