Texas Instruments Corporation

Texes Instruments Incorporated

Alwin J Tsao

Amitava Chatterjee

Seetharaman Sridhar

Kayvan Sadra

Xiang-Zheng Bo

Douglas Ticknor Grider

Vikas I Gupta

Greg Charles Baldwin

David B Spratt

Timothy Alan Rost

Stephen Keith Heinrich-Barna

Douglas P Verret

E Ajith Amerasekera

Gregory Charles Baldwin

Brian Edward Hornung

Eddie Hearl Breashears

Lahir Shaik Adam

Purushothaman Srinivasan

Mahalingam Nandakumar

Byron Lovell Williams

Satyavolu Srinivas Papa Rao

Hisashi Shichijo

Antonio Luis Pacheco Rotondaro

Kenneth D Brennan

Darius Lammont Crenshaw

Shaoping Tang

Noel M Russell

Manuel A Quevedo-Lopez

Majid Movahed Mansoori

Bobby D Strong

Jong Shik Yoon

Steven Alan Lytle

Paul Matthew Gillespie

Brian Ashley Smith

Christopher Lyle Borst

Murlidhar Bashyam

Douglas Newman

The present disclosure provides a method for adjusting implant parameter conditions in semiconductor processing by wafer and by wafer zone using in-line measurements from previous operations and a feed-forward computer model. The feed-forward model is based on a sensitivity map of in-line measured data and its effect of electrical performance. Feed-forward computer models that adjust implant parameters by wafer and by zone improve both wafer-to-wafer and within wafer electrical uniformity in semiconductor devices.

Variable implant and wafer-level feed-forward for dopant dose optimization

An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor.

High tilt angle plus twist drain extension implant for CHC lifetime improvement

An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant.

Deep collector vertical bipolar transistor with enhanced gain

An integrated circuit containing a well resistor has STI field oxide and resistor dummy active areas in the well resistor. STI trenches are etched and filled with trench fill dielectric material. The trench fill dielectric material is removed from over the active areas by a CMP process, leaving STI field oxide in the STI trenches. Subsequently, dopants are implanted into a substrate in the well resistor area to form the well resistor. An integrated circuit containing a polysilicon resistor has STI field oxide and resistor dummy active areas in an area for the polysilicon resistor. A layer of polysilicon is formed and planarized by a CMP process. A polysilicon etch mask is formed over the CMP-planarized polysilicon layer to define the polysilicon resistor. A polysilicon etch process removes polysilicon in areas exposed by the polysilicon etch mask, leaving the polysilicon resistor.

Well resistors and polysilicon resistors

An integrated circuit, in which a minimum gate length of low-noise NMOS transistors is less than twice a minimum gate length of logic NMOS transistors, is formed by: forming gates of the low-noise NMOS transistors concurrently with gates of the logic NMOS transistors, forming a low-noise NMDD implant mask which exposes the low-noise NMOS transistors and covers the logic NMOS transistors and logic PMOS transistors, ion implanting n-type NMDD dopants and fluorine into the low-noise NMOS transistors and limiting p-type halo dopants to less than 20 percent of a corresponding logic NMOS halo dose, removing the low-noise NMDD implant mask, forming a logic NMDD implant mask which exposes the logic NMOS transistors and covers the low-noise NMOS transistors and logic PMOS transistors, ion implanting n-type NMDD dopants and p-type halo dopants, but not implanting fluorine, into the logic NMOS transistors, and removing the logic NMDD implant mask.

Method for 1/F noise reduction in NMOS devices

The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.

Application of different isolation schemes for logic and embedded memory

The present invention provides a tri-gate lower power device and method for fabricating that tri-gate semiconductor device. The tri-gate device includes a first gate [] located over a high voltage gate dielectric [] within a high voltage region [], a second gate [] located over a low voltage gate dielectric [] within a low voltage core region [] and a third gate [] located over an intermediate core oxide [] within an intermediate core region []. One method of fabrication includes forming a high voltage gate dielectric layer [] over a semiconductor substrate [], implanting a low dose of nitrogen [] into the semiconductor substrate [] in a low voltage core region [], and forming a core gate dielectric layer [] over the low voltage core region [], including forming an intermediate core gate dielectric layer [] over an intermediate core region [

Tri-gate low power device and method for manufacturing the same

A method () of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A sidewall spacer () is formed against an edge () of a layer of bottom electrode/copper diffusion barrier material (), an edge () of a layer of capacitor dielectric material () and at least some of an edge () of a layer of top electrode material. The sidewall spacer () is dielectric or non-conductive and mitigates 'shorting' currents that can develop between the plates as a result of copper diffusion. Bottom electrode diffusion barrier material () mitigates copper diffusion and/or copper drift, thereby reducing the likelihood of premature device failure.

Metal insulator metal (MIM) capacitor fabrication with sidewall spacers and aluminum cap (ALCAP) top electrode

The present invention pertains to formation of a transistor in a manner that mitigates overlap capacitances, thereby facilitating, among other things, enhanced switching speeds. More particularly, a gate stack of the transistor is formed to include an optional layer of poly-SiGe and a layer of poly-Si, where at least one or the layers comprises carbon. The stack may also include a polysilicon seed layer that can also comprise carbon. The carbon changes the components of sidewall passivation materials and affects etch rates during an etching process, thereby facilitating isotropic etching. The changed passivation materials coupled with an enhanced sensitivity of the poly-SiGe and carbon-doped poly-SiGe layer to an etchant utilized in the etching process causes the stack to have a notched appearance. The tapered configuration of the gate stack provides little, if any, area for dopants that may migrate under the gate structure to overlap the conductive layers in the stack, and thus mitigates the opportunity for overlap capacitances to arise.

Method to reduce transistor gate to source/drain overlap capacitance by incorporation of carbon

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Garland, TX, United States of America

Alwin J Tsao