Intel Corporation

Alvin Shing Chye Goh

Christopher P Mozak

Steven T Taylor

Vui Yong Liew

Terrence Huat Hin Tan

Wei Ming Lim

Madhu Rao

Kim Leong Lee

Yah Chen Chew

Techniques for command bus training to a memory device includes triggering a memory device to enter a first or a second command bus training mode, outputting a command/address (CA) pattern via a command bus and compressing a sampled CA pattern returned from the memory device based on whether the memory device was triggered to be in the first or the second command bus training mode.

Techniques for command bus training to a memory device

Methods and apparatus for predictable protocol aware testing on a memory interface are are shown. An apparatus to support a protocol aware testing on a memory interface may include a digital controller to receive a plurality of read request commands from a unit under test. The digital controller further to hold the plurality of read request commands while a hold signal has a first value, and to sequentially release individual read request commands of the plurality of read request commands while to the hold signal has a second value. The digital controller further to provide input/output (I/O) commands to an output based on a particular released read request command of the plurality of read request commands. Timing of provision of the I/O commands is deterministic based on a transition of the hold signal from the first value to the second value.

Methods and apparatus for predictable protocol aware testing on memory interface

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Bayan Lepas, Malaysia

Alvin Shing Chye Goh