Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Alvin Joshua

Hardwell Chibvongodze

Akitomo Nakayama

Yuki Kuniyoshi

Zhixin Cui

Akira Hanasaka

Technology is for managing non-volatile memory such as NAND memory. A memory system that programs the threshold voltages (Vt) of transistors on NAND strings to enable selection of sub-blocks without physically separate select lines in a block. A first set of one or more transistors on a NAND string may be programmed to a higher Vt and a second set of one or more transistors on the NAND string may be programmed to a lower Vt. Each NAND string in a sub-block may have the same pattern of high Vt and low Vt transistors. However, each sub-block has its own pattern of high Vt and low Vt transistors to enable selection of the sub-blocks. To select NAND strings in a sub-block, a high voltage is applied to a first set of the conductive lines and a low voltage is applied to a second set of the conductive lines.

Artificial select gate cut for NAND

On memory die and other circuits, some parts may operate at a VDD logic level while other elements operate at a higher logic level, such as at or near the die's supply level VSUP. To reduce power consumption and increase operating speeds, VDD levels are moving to increasingly lower voltages. To raise the logic signal from the lower level to the higher, level shifters can be used. However, as the gap between the supply level VSUP and VDD widens, it can become difficult for a level shifter to reliably raise a logic signal operating at the VDD level to the VSUP level. The address this problem, the following introduces a small charge pump to boost the input logic signals for level shifter circuits to allow them to reliably generate an output logic signal at the VSUP level from an input logic signal at low VDD levels.

Mini-pump level shifter for robust switching operation under low VDD environment

Systems and methods disclosed herein provide a modulation scheme that enables memory dies of a memory stack to occupy a shared data line in parallel, which increases data throughput within the memory stack. The systems and methods disclosed herein modulate data input/output (I/O) signals to convert the data I/O signals from a first domain to a second domain. Each data I/O signal corresponds to a memory die. The data I/O signals are separated onto channels that are non-overlapping in the second domain and are supplied simultaneously to a data line. By separating the data I/O signal onto non-overlapping channels, the plurality of memory dies can be operated in parallel at approximately the same time. In an illustrative example, the first domain is the time domain and the second domain is the frequency domain, which the channels being separate, non-overlapping frequency bands.

Growing community of inventors

Fujisawa, Japan

Alvin Joshua