Faraday Technology Corporation

Alvin Hsin-Hung Chen

Kun-Cheng Wu

Jia-Jio Huang

Chih-Yang Peng

Hanping Chen

Jim Jyh-Herng Wang

A fast methodology and system to characterize setup/hold time for analog IPs are provided. Partial circuits of clock and data paths are simulated instead of the simulation of entire IPs. The partial circuits include all those paths of clock pin and data input pins before reaching first level DFF. This methodology includes multi-path searching of hierarchical SPICE netlist for the path of clock pin and data pins, so as to reduce the circuit subset, merge the paths of clock pin and the data pins, and characterize the setup/hold time for the analog IP. The paths of data pins and clock pin before DFF are used for setup/hold time characterization.

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Kaohsiung, Taiwan

Alvin Hsin-Hung Chen