International Business Machines Corporation

Cisco Technology, Inc.

Alvar Antonio Dean

Sebastian Theodore Ventrone

Kenneth Joseph Goodnow

David James Hathaway

John Maxwell Cohn

Patrick Edward Perry

Scott Alan Tetreault

Wilbur David Pricer

Amir H Farrahi

Claude Louis Bertin

Thomas M Lepsic

William R Tonti

Scott Whitney Gould

David E Lackey

Jagannathan Narasimhan

Charles N Choukalos

John T Chapman

Joseph Andrew Iadanza

Anthony Richard Bonaccio

Michael J Healy

Stephen William Mahin

John P Prokopik

Richard J Santarpio

William Robert Patrick Tonti

Jerry D Hayes

Susan K Lichtensteiger

Marc Raymond Faucher

Larry Wissel

Paul T Gutwin

Roger Paul Gregor

Mircea R Stan

Emory D Keller

Paul H Bergeron

Keith M Carrig

John Bula

Kenneth Torino

Dana J Thygesen

Stephen B Barrett

John W Goetz

Harold E Reindel

David C Garrett

A wideband cable modem system increases available bandwidth of a single channel by encoding a data stream into wideband packets. The wideband packets are associated with a logical wideband channel that extends over multiple physical downstream cable channels.

Wideband cable system

A test board includes a plurality of sockets for connection to a plurality of integrated circuit chips to be tested. A test control device on the board turns on at least one test engine for testing the plurality of chips simultaneously. A checking circuit verifies the functionality of each chip by comparing outputs of chips with each other or with a golden chip. Failing Chips are disconnected from further testing and passing or failing chips are recorded.

Test system for integrated circuits

An electrical wiring structure and a computer system for designing the electrical wiring structure. The electrical wiring structure includes a wire pair. The wire pair includes a first wire and a second wire. The second wire is slated for being tri-stated. The wire pair has a same-direction switching probability &#x3c6;per clock cycle that is no less than a pre-selected minimum same-direction switching probability &#x3c6;or has an opposite-direction switching probability &#x3c6;per clock cycle that is no less than a pre-selected minimum opposite-direction switching probability &#x3c6;. The first wire and the second wire satisfies at least one mathematical relationship involving Land Wwhere Wis defined as a spacing between the first wire and the second wire, and Lis defined as a common run length of the first wire and the second wire.

Wiring optimizations for power

A test board includes a plurality of sockets for connection to a plurality of integrated circuit chips to be tested. A test control device on the board turns on at least one test engine for testing the plurality of chips simultaneously. A checking circuit verifies the functionality of each chip by comparing outputs of chips with each other or with a golden chip. Failing chips are disconnected from further testing and passing or failing chips are recorded.

An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.

A differential sinusoidal signal pair is generated on an integrated circuit (IC). The differential sinusoidal signal pair is distributed to clock receiver circuits, which may be differential amplifiers. The clock receiver circuits receive the differential sinusoidal signal pair and convert the differential sinusoidal pair to local clock signals. Power consumption and noise generation are reduced as compared to conventional clock signal distribution arrangements.

Clock signal distribution utilizing differential sinusoidal signal pair

A way of dynamically modifying error recovery on a communications controller to operate at the lowest power mode allowed by current error rate conditions. When operating conditions are good and a small number of errors are detected, a low power error detection/correction mode is entered saving battery life. The low power error correction mechanism runs at a slower frequency and lower power than the high power mechanism and maintains the same data rate for the controller, thus saving power. Selecting the controller error (power) mode may be externally, such as by a person using a control dial on a cellular telephone when the voice data gets too noisy. Alternatively, the selection can be automatic, a critical error level detector internally making the selection.

Low-power critical error rate communications controller

Both logical and physical construction of voltage islands is disclosed. A semiconductor chip design is partitioned into &ldquo;bins&rdquo;, which are areas of the design. In this way, a semiconductor chip design may be &ldquo;sliced&rdquo; into various areas and the areas may then be assigned to various voltage levels. Each bin may be thought of as a voltage island. Circuits in the design can be added to or removed from the various bins, thereby increasing or decreasing the speed and power of the circuits: the speed and power increase if a circuit is placed into a bin assigned a higher voltage, and the speed and power decrease if a circuit is placed into a bin having a lower voltage. The size and location of the bins may also be changed. By iterating these steps, the optimum power consumption may be met while still meeting speed constraints and other criteria. The present invention is applicable to any placement environment, such as an annealing placement tool, that proceeds through successive refinement of the locations of the circuits on the design and in which the placement process may be interrupted to make changes in placement of the logic.

Concurrent logical and physical construction of voltage islands for mixed supply voltage designs

In integrated circuit (IC) designs, a component of power consumed may be represented as Power&equals;&frac12; FCV , where C is the load capacitance being driven by a source cell, F is the switching frequency of the source cell, and V is the total output voltage swing. However, not every signal value generated by a source cell is required to propagate to all the sink cells connected to the source for every clock cycle of a chip. Accordingly, an isolate cell is inserted in a net (wire) connecting a source cell to at least one sink cell, to de-couple the at least one sink cell and a portion of the net from the source cell when a signal output by the source need not propagate. Due to the de-coupling, the load capacitance associated with the at least one sink and net portion is not experienced by the source cell for such signals. Accordingly, overall IC power consumption is reduced.

Method and apparatus for reducing power consumption in VLSI circuit designs

A method for reducing leakage power of a logic network comprising the steps of: using (observability) don't care information to identify &ldquo;sleep states&rdquo; for individual nets; determining based on probabilistic analysis at least one net in which expected power consumption will be reduced by forcing a net to a particular value during at least a portion of a &ldquo;sleep state&rdquo;; and forcing the determined net to the determined value determined portion of that &ldquo;sleep state&rdquo;.

System and method for inserting leakage reduction control in logic circuits

A method of testing a digital logic circuit comprises first providing a logic circuit having a plurality of interconnected circuits each having an input and an output; determining a gate level representation of the logic circuit including test nets for determining faults in the circuit; and identifying a portion of the nets which are most difficult to test, including nets which are most difficult to control and nets which are most difficult to observe. The method then includes inserting into the logic circuit control latches for nets which are determined to be most difficult to control and inserting into the logic circuit observation latches for nets which are determined to be most difficult to observe. Using the inserted control latches and observation latches, the method further includes testing the nets which are determined to be most difficult to control and nets which are hardest to observe and determining faults in the circuit. As a result of the method of the present invention, testing is completed in a time faster than if the nets were tested without the control latches and the observation latches. The portion of the nets which are most difficult to test are preferably identified by overall test time impact, and the nets having longest test times are determined to be most difficult to control and most difficult to observe.

Method of automatic latch insertion for testing application specific integrated circuits

A method and structure of clock optimization including creating an initial placement of clock feeding circuits according to clock signal requirements; identifying clusters of the clock feeding circuits, wherein each cluster includes a distinct clock signal supply device to which each clock feeding circuit within the cluster is connected; changing pin connections between the clock feeding circuits and clock signal supply devices to switch selected ones of the clock feeding circuits to different clusters to reduce lengths of wires between the clock feeding circuits and the clock signal supply devices within each cluster; and adjusting positions of the clock feeding circuits within design constraints to further reduce the lengths of the wires.

Latch clustering for power optimization

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Groton, MA, United States of America

Alvar Antonio Dean