Intel Corporation

Altug Koker

Abhishek R Appu

Joydeep Ray

Balaji Vembu

Prasoonkumar Surti

Vasanth Ranganathan

Subramaniam M Maiyuran

Kamal Sinha

Elmoustapha Ould-Ahmed-Vall

Sanjeev S Jahagirdar

Kiran Chand Veernapu

Travis T Schluessler

Nicolas C Galoppo Von Borries

Murali Ramadoss

Dukhwan Kim

Linda L Hurd

Ankur N Shah

Ben J Ashbaugh

Varghese George

David M Puffer

Aravindh V Anantaraman

Lakshminarayanan Striramassarma

Feng Chen

Narayan Srinivasa

Xiaoming Chen

Wenyin Fu

Pattabhiraman K

Eriko Nurvitadhi

Sara S Baghsorkhi

Michael S Strickland

Farshad Akhbari

Anbang Yao

John Charles Weast

Nadathur Rajagopalan Satish

Nikos Kaburlasos

Bhushan M Borole

Ping Tak Tang

Jeffery S Boles

Rajkishore Barik

Tsung-Han Lin

Mike MacPherson

Justin E Gottschlich

Adam T Lake

James A Valerio

Aditya Navale

Josh B Mastronarde

Guei-Yuan Lueh

Devan Burke

Chandrasekaran Sakthivel

John H Feit

Jonathan Kennedy

Tatiana Shpeisman

Liwei Ma

Michael Apodaca

Niranjan L Cooray

Jacek Kwiatkowski

Karthik Vaidyanathan

Scott R Janus

Kai Xiao

Gabor Liktor

James M Holland

Peter L Doyle

Stanley J Baran

Eric C Samson

Kun Tian

Hugues Labbe

Thomas A Piazza

Narayan Biswal

Abhishek Venkatesh

Sanu K Mathew

Mark A Anders

Himanshu Kaul

Jill MacDonald Boyce

Ingo Wald

Tomer Bar-On

Rajesh M Sankaran

Lidong Xu

Deepak Shashidhar Vembar

Zhi Hu Wang

Atsuo Kuwahara

Mahesh S Natu

Selvakumar Panneer

Sang-Hee Lee

Christopher J Hughes

Tomas G Akenine-Moller

Changliang Wang

Zhi Jun Wang

Gilbert A Neiger

Mark T Bohr

Muhammad M Khellah

Ali-Reza Adl-Tabatabai

Andrew V Anderson

Hong Jiang

Ravishankar Iyer

Blaise B Fanning

Swaminathan Sivakumar

Jason Daniel Tanner

James B Crossland

Philip R Lantz

Wilfred Gomes

An apparatus to facilitate optimization of a neural network (NN) is disclosed. The apparatus includes optimization logic to define a NN topology having one or more macro layers, adjust the one or more macro layers to adapt to input and output components of the NN and train the NN based on the one or more macro layers.

Neural network optimization mechanism

In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

Engine to enable high speed context switching via on-die storage

In one embodiment, a processor includes: a graphics processor to execute a workload; and a power controller coupled to the graphics processor. The power controller may include a voltage ramp circuit to receive a request for the graphics processor to operate at a first performance state having a first operating voltage and a first operating frequency and cause an output voltage of a voltage regulator to increase to the first operating voltage. The voltage ramp circuit may be configured to enable the graphics processor to execute the workload at an interim performance state having an interim operating voltage and an interim operating frequency when the output voltage reaches a minimum operating voltage. Other embodiments are described and claimed.

System, apparatus and method for increasing performance in a processor during a voltage ramp

Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.

Dynamic memory reconfiguration

An apparatus to facilitate a system-on-a-chip (SoC) architecture for low power state communication is disclosed. The apparatus includes a low power state fabric to provide a low power state path that avoids compute processing resources of the apparatus, and a low power state agent circuitry communicably coupled to the low power state fabric to update, in response to initiation of a low power state in the apparatus, a configuration of routers of the low power state fabric to utilize the low power state path provided by the low power state fabric, and to route memory transactions to the low power state path while the apparatus is in the low power state.

System-on-a-chip (SoC) architecture for low power state communication

In a further embodiment, a system on a chip integrated circuit (SoC) is provided that includes an active base die including a first cache memory, a first die mounted on and coupled with the active base die, and a second die mounted on the active base die and coupled with the active base die and the first die. The first die includes an interconnect fabric, an input/output interface, and an atomic operation handler. The second die includes an array of graphics processing elements and an interface to the first cache memory of the active base die. At least one of the graphics processing elements are configured to perform, via the atomic operation handler, an atomic operation to a memory device.

Atomic handling for disaggregated 3D structured SoCs

One embodiment provides a general-purpose graphics processing unit comprising a dynamic precision floating-point unit including a control unit having precision tracking hardware logic to track an available number of bits of precision for computed data relative to a target precision, wherein the dynamic precision floating-point unit includes computational logic to output data at multiple precisions.

Compute optimizations for low precision machine learning operations

Embodiments are generally directed to memory prefetching in multiple GPU environment. An embodiment of an apparatus includes multiple processors including a host processor and multiple graphics processing units (GPUs) to process data, each of the GPUs including a prefetcher and a cache; and a memory for storage of data, the memory including a plurality of memory elements, wherein the prefetcher of each of the GPUs is to prefetch data from the memory to the cache of the GPU; and wherein the prefetcher of a GPU is prohibited from prefetching from a page that is not owned by the GPU or by the host processor.

Prefetch status notification for memory prefetching

Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides a parallel processor comprising a processing cluster coupled with the cache memory. The processing cluster includes a plurality of multiprocessors coupled with a data interconnect, where a multiprocessor of the plurality of multiprocessors includes a tensor core configured to load tensor data and metadata associated with the tensor data from the cache memory, wherein the metadata indicates a first numerical transform applied to the tensor data, perform an inverse transform of the first numerical transform, perform a tensor operation on the tensor data after the inverse transform is performed, and write output of the tensor operation to a memory coupled with the processing cluster.

Systolic arithmetic on sparse data

In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

Dynamic precision for neural network compute operations

Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width adjustment based on throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamically configurable bus widths and frequencies.

Interconnect fabric link width reduction to reduce instantaneous power consumption

Embodiments described herein provide techniques to facilitate instruction-based control of memory attributes. One embodiment provides a graphics processor comprising a processing resource, a memory device, a cache coupled with the processing resources and the memory, and circuitry to process a memory access message received from the processing resource. The memory access message enables access to data of the memory device. To process the memory access message, the circuitry is configured to determine one or more cache attributes that indicate whether the data should be read from or stored the cache. The cache attributes may be provided by the memory access message or stored in state data associated with the data to be accessed by the access message.

Implicit fence for write messages

An apparatus to facilitate efficient data sharing for graphics data processing operations is disclosed. The apparatus includes a processing resource to generate a stream of instructions, an L1 cache communicably coupled to the processing resource and comprising an on-page detector circuit to determine that a set of memory requests in the stream of instructions access a same memory page; and set a marker in a first request of the set of memory requests; and arbitration circuitry communicably coupled to the L1 cache, the arbitration circuitry to route the set of memory requests to memory comprising the memory page and to, in response to receiving the first request with the marker set, remain with the processing resource to process the set of memory requests.

Efficient data sharing for graphics data processing operations

Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to detect zero value elements within a vector or a set of packed data elements output by a processing resource and generate metadata to indicate a location of the zero value elements within the plurality of data elements.

Sparse optimizations for a matrix accelerator architecture

An apparatus and method are described for managing data which is biased towards a processor or a GPU. For example, an apparatus comprises a processor comprising one or more cores, one or more cache levels, and cache coherence controllers to maintain coherent data in the one or more cache levels; a graphics processing unit (GPU) to execute graphics instructions and process graphics data, wherein the GPU and processor cores are to share a virtual address space for accessing a system memory; a GPU memory addressable through the virtual address space shared by the processor cores and GPU; and bias management circuitry to store an indication for whether the data has a processor bias or a GPU bias, wherein if the data has a GPU bias, the data is to be accessed by the GPU without necessarily accessing the processor's cache coherence controllers.

Apparatus and method for managing data bias in a graphics processing architecture

Growing community of inventors

El Dorado Hills, CA, United States of America

Altug Koker