Intel Corporation

Altug Koker

Abhishek R Appu

Joydeep Ray

Balaji Vembu

Prasoonkumar Surti

Vasanth Ranganathan

Subramaniam M Maiyuran

Kamal Sinha

Elmoustapha Ould-Ahmed-Vall

Sanjeev S Jahagirdar

Kiran Chand Veernapu

Travis T Schluessler

Nicolas C Galoppo Von Borries

Murali Ramadoss

Dukhwan Kim

Linda L Hurd

Ankur N Shah

Ben J Ashbaugh

Varghese George

David M Puffer

Aravindh V Anantaraman

Lakshminarayanan Striramassarma

Narayan Srinivasa

Feng Chen

Xiaoming Chen

Wenyin Fu

John Charles Weast

Sara S Baghsorkhi

Pattabhiraman K

Nikos Kaburlasos

Eriko Nurvitadhi

Michael S Strickland

Farshad Akhbari

Anbang Yao

Nadathur Rajagopalan Satish

Ping Tak Tang

Jeffery S Boles

Justin E Gottschlich

Mike B Macpherson

Rajkishore Barik

Tsung-Han Lin

Mike MacPherson

Adam T Lake

Aditya Navale

James A Valerio

Guei-Yuan Lueh

Chandrasekaran Sakthivel

Devan Burke

Josh B Mastronarde

John H Feit

Jonathan Kennedy

Liwei Ma

Tatiana Shpeisman

Michael Apodaca

Niranjan L Cooray

Jacek Kwiatkowski

Karthik Vaidyanathan

Scott R Janus

Kai Xiao

James M Holland

Gabor Liktor

Peter L Doyle

Stanley J Baran

Eric C Samson

Kun Tian

Hugues Labbe

Thomas A Piazza

Narayan Biswal

Abhishek Venkatesh

Sanu K Mathew

Mark A Anders

Himanshu Kaul

Jill MacDonald Boyce

Lidong Xu

Ingo Wald

Tomer Bar-On

Rajesh M Sankaran

Deepak Shashidhar Vembar

Zhi Hu Wang

Atsuo Kuwahara

Mahesh S Natu

Changliang Wang

Selvakumar Panneer

Sang-Hee Lee

Christopher J Hughes

Tomas G Akenine-Moller

Zhi Jun Wang

Gilbert A Neiger

Mark T Bohr

Muhammad M Khellah

Hong Jiang

Ali-Reza Adl-Tabatabai

Andrew V Anderson

Ravishankar Iyer

Blaise B Fanning

Swaminathan Sivakumar

Jason Daniel Tanner

Wilfred Gomes

James B Crossland

Philip R Lantz

Embodiments described herein are generally directed to improvements relating to power, latency, bandwidth and/or performance issues relating to GPU processing/caching. According to one embodiment, a system includes a producer intellectual property (IP) (e.g., a media IP), a compute core (e.g., a GPU or an AI-specific core of the GPU), a streaming buffer logically interposed between the producer IP and the compute core. The producer IP is operable to consume data from memory and output results to the streaming buffer. The compute core is operable to perform AI inference processing based on data consumed from the streaming buffer and output AI inference processing results to the memory.

Graphics processing unit processing and caching improvements

A system includes a compression engine that stores the compression format information embedded in the compressed data. The compression format information can be included in a header that includes compression control surface (CCS) information. The system includes a shared memory to store compressed data for multiple hardware pipelines, where blocks of the compressed data have a common memory footprint and the compression header. The compression engine can compress data to store in the shared memory including generation of the header. The compression engine can decompress data read from the shared memory, including identification of the compression format from the header.

Unified stateless compression system for universally consumable compression

A mechanism is described for detecting, at training time, information related to one or more tasks to be performed by the one or more processors according to a training dataset for a neural network, analyzing the information to determine one or more portions of hardware of a processor of the one or more processors that is configurable to support the one or more tasks, configuring the hardware to pre-select the one or more portions to perform the one or more tasks, while other portions of the hardware remain available for other tasks, and monitoring utilization of the hardware via a hardware unit of the graphics processor and, via a scheduler of the graphics processor, adjusting allocation of the one or more tasks to the one or more portions of the hardware based on the utilization.

Coordination and increased utilization of graphics processors during inference

In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.

Regional adjustment of render rate

An apparatus to facilitate optimization of a neural network (NN) is disclosed. The apparatus includes optimization logic to define a NN topology having one or more macro layers, adjust the one or more macro layers to adapt to input and output components of the NN and train the NN based on the one or more macro layers.

Neural network optimization mechanism

In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

Engine to enable high speed context switching via on-die storage

In one embodiment, a processor includes: a graphics processor to execute a workload; and a power controller coupled to the graphics processor. The power controller may include a voltage ramp circuit to receive a request for the graphics processor to operate at a first performance state having a first operating voltage and a first operating frequency and cause an output voltage of a voltage regulator to increase to the first operating voltage. The voltage ramp circuit may be configured to enable the graphics processor to execute the workload at an interim performance state having an interim operating voltage and an interim operating frequency when the output voltage reaches a minimum operating voltage. Other embodiments are described and claimed.

System, apparatus and method for increasing performance in a processor during a voltage ramp

Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.

Dynamic memory reconfiguration

An apparatus to facilitate a system-on-a-chip (SoC) architecture for low power state communication is disclosed. The apparatus includes a low power state fabric to provide a low power state path that avoids compute processing resources of the apparatus, and a low power state agent circuitry communicably coupled to the low power state fabric to update, in response to initiation of a low power state in the apparatus, a configuration of routers of the low power state fabric to utilize the low power state path provided by the low power state fabric, and to route memory transactions to the low power state path while the apparatus is in the low power state.

System-on-a-chip (SoC) architecture for low power state communication

In a further embodiment, a system on a chip integrated circuit (SoC) is provided that includes an active base die including a first cache memory, a first die mounted on and coupled with the active base die, and a second die mounted on the active base die and coupled with the active base die and the first die. The first die includes an interconnect fabric, an input/output interface, and an atomic operation handler. The second die includes an array of graphics processing elements and an interface to the first cache memory of the active base die. At least one of the graphics processing elements are configured to perform, via the atomic operation handler, an atomic operation to a memory device.

Atomic handling for disaggregated 3D structured SoCs

One embodiment provides a general-purpose graphics processing unit comprising a dynamic precision floating-point unit including a control unit having precision tracking hardware logic to track an available number of bits of precision for computed data relative to a target precision, wherein the dynamic precision floating-point unit includes computational logic to output data at multiple precisions.

Compute optimizations for low precision machine learning operations

Embodiments are generally directed to memory prefetching in multiple GPU environment. An embodiment of an apparatus includes multiple processors including a host processor and multiple graphics processing units (GPUs) to process data, each of the GPUs including a prefetcher and a cache; and a memory for storage of data, the memory including a plurality of memory elements, wherein the prefetcher of each of the GPUs is to prefetch data from the memory to the cache of the GPU; and wherein the prefetcher of a GPU is prohibited from prefetching from a page that is not owned by the GPU or by the host processor.

Prefetch status notification for memory prefetching

Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides a parallel processor comprising a processing cluster coupled with the cache memory. The processing cluster includes a plurality of multiprocessors coupled with a data interconnect, where a multiprocessor of the plurality of multiprocessors includes a tensor core configured to load tensor data and metadata associated with the tensor data from the cache memory, wherein the metadata indicates a first numerical transform applied to the tensor data, perform an inverse transform of the first numerical transform, perform a tensor operation on the tensor data after the inverse transform is performed, and write output of the tensor operation to a memory coupled with the processing cluster.

Systolic arithmetic on sparse data

In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

Dynamic precision for neural network compute operations

Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width adjustment based on throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamically configurable bus widths and frequencies.

Interconnect fabric link width reduction to reduce instantaneous power consumption

Growing community of inventors

El Dorado Hills, CA, United States of America

Altug Koker