Rockwell Collins, Inc.

Altin E Pelteku

Raymond Zanoni

Oliver S King

Jonathan A Lovseth

Orion D Davies

Jerzy K Richter

A filter apparatus is disclosed. The filter apparatus may include a plurality of dielectric layers. The plurality of dielectric layers may include one or more first dielectric layers formed of a first dielectric material and one or more second dielectric layers formed of a second dielectric material. The second dielectric material of the one or more second dielectric layers being different than the first dielectric material of the one or more first dielectric layers. The filter apparatus may further include one or more thin-film metal layers arranged between at least one dielectric layer of the plurality of dielectric layers and an additional dielectric layer of the plurality of dielectric layers.

Dielectric and thin film floating metal stacking for embedded tunable filtering of high frequency signals

A photonic analog to digital converter (pADC) includes an electronic I/Q generator, an optical sampler, and an optical detector. The electronic I/Q generator is configured to receive an RF signal and to generate an electronic in-phase signal I and an electronic quadrature-phase signal Q based on the received RF signal. The optical sampler includes one or more optical intensity modulators configured to receive the electronic I and Q signals from the electronic I/Q generator, and to modulate optical pulses to provide modulated optical I and Q signals based on the received electronic I and Q signals from the electronic I/Q generator. The optical detector includes a plurality of photodetectors, and is arranged to receive the modulated optical I and Q signals from the optical sampler and to convert the modulated optical I and Q signals into modulated electronic I and Q signals.

Photonic direct sampling digital receiver

A voltage-mode integrate-and-dump photonic ADC front-end circuit includes a current integrator for immediately integrating current pulses onto a capacitor voltage, the current pulses converted by photodetectors from optical data pulses corresponding to a received analog input signal. The circuit may include dampeners for reducing voltage ringing and resulting intersymbol interference (ISI) to preserve SNR at high data rates. The integrating capacitor may be discharged by a reset switch based on clock signals generated by a master clock; the reset switch may include a pulse width controller enabling the integrating capacitor to track and hold the integrated voltage, rather than downstream sample-and-hold amplifiers. Quantizers and other signal processors generate digital signal output by sampling and digitizing the integrated voltage output of the current integrator.

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Severna Park, MD, United States of America

Altin E Pelteku