Nxp B.v.

Alphons Litjes

Erik Olieman

Cristian Pavao Moreira

Alexander Vogt

Ibrahim Candan

Michael Todd Berens

Hendrik Johannes Bergveld

Robert Van Veldhoven

Leon Van Der Dussen

A SAR ADC includes a DAC, a comparator and SAR circuitry, where the DAC includes MSBs encoded with first capacitors; a mismatch error shaping capacitor coupled to the MSBs; LSBs encoded with second capacitors, where a first switch set couples bottom capacitor plates of the first capacitors and the mismatch error shaping capacitor to receive an analog input voltage, a high reference voltage, or a low reference voltage in response to first DAC feedback control signals, wherein a second switch set couples bottom capacitor plates of the second capacitors to receive the high reference voltage or the low reference voltage in response to second DAC feedback control signals, and wherein the SAR circuitry is configured to feedback a mismatch error value from a previous SAR conversion cycle to the LSBs sub-DAC during a current sampling cycle.

SAR ADC with bottom-plate sampling and mismatch error shaping

Systems and methods are provided for performing both wireless communications and wireless sensing in combination. The systems include at least a first base station having at least one antenna device where the antenna device includes a beamformer control unit that uses a modifiable lookup table to control beam characteristics. The system may send a first set of electromagnetic sensing beams to a first environmental area within a field of view of the at least one antenna device to detect environmental objects within the environmental area. Based on data received by the antenna device, the system may generate a modified lookup table.

Apparatus and methods for optimizing combined sensing and communications systems

An analog to digital converter including a digital to analog converter (DAC), a comparator, and a controller. The DAC includes a sample node and a capacitor array controlled by a digital control input. The comparator compares a voltage of the sample node with a reference voltage to generate a comparison value. The controller presets the digital control input, prompts the DAC to sample the input voltage onto the sample node, resets the digital control input, and performs a conversion by successively adjusting the digital control input based on the comparison value to determine a digital output. A preset value is subtracted from the digital output to provide an adjusted digital output. A sample predictor predicts the next sample to determine the preset value used to adjust the sample node within a full scale range after DAC reset.

System and method of extending input range of analog to digital converter

Systems and methods for performing both wireless communications and wireless sensing in combination are disclosed herein. In one example embodiment, the method includes sending, from a first antenna device of a base station (BS), a plurality of first wireless communication signals respectively during a first plurality of time periods associated respectively with a first plurality of symbols and also a plurality of first wireless sensing signals respectively during a second plurality of time periods associated respectively with a second plurality of symbols. Also, the method includes receiving, at the antenna device, a plurality of second wireless communication signals respectively during a third plurality of time periods associated respectively with a third plurality of symbols and also a plurality of second wireless sensing signals respectively during the second plurality of time periods. The second plurality of time periods are interleaved among respective pairs of the first plurality of time periods.

System and method for combined performing of wireless communication and sensing

Systems and methods for performing both wireless communications and wireless sensing in combination are disclosed herein. In one example embodiment, the system includes a base station (BS) including each of at least one antenna device including a first antenna device and at least one control unit. The control unit includes an input port coupled at least indirectly to the first antenna device, an output port, and a controllable circuit including each of a spillover cancellation circuit and a bypass circuit. The BS is configured to operate in each of a communication mode and a sensing mode. When the BS operates in the sensing mode, the spillover cancellation circuit of the controllable circuit is enabled and performs spillover cancellation. When the BS operates in a communication mode, the bypass circuit operates so that the spillover cancellation circuit is bypassed or otherwise does not affect how the output signal is generated.

In an embodiment, there is provided a battery management method for a vehicle comprising a plurality of batteries. According to another embodiment there is a control unit for performing the battery management method. The battery management method comprising detecting an incoming hazard; predicting an impact of the incoming hazard from one or more sensors coupled to the vehicle; determining a course of action to be taken in response to the predicted impact; and controlling one or more batteries of the plurality of batteries according to the determined course of action.

Battery management system and method

A capacitive sampling circuit comprises: a first-differential-input-terminal, configured to receive a first one of a pair of differential-input-signals; a second-differential-input-terminal, configured to receive the other one of the pair of differential-input-signals; a capacitive-circuit-output-terminal, configured to provide a sampled-output-signal; a plurality of first-sampling-capacitors, each having a first-plate and a second-plate; a plurality of reference-voltage-terminals, each configured to receive a respective reference-voltage; and a first-capacitor-first-plate-switching-block configured to selectively connect the first-plate of each of the plurality of first-sampling-capacitors to either: (i) the first-differential-input-terminal; or (ii) a respective one of the plurality of reference-voltage-terminals; and a first-capacitor-second-plate-switch, configured to selectively connect or disconnect the second-plate of each of the plurality of first-sampling-capacitors to the second-differential-input-terminal.

Capacitive sampling circuit

Embodiments of an analog-to-digital converter (ADC), resistive digital-to-analog converter (DAC) circuits, and methods of operating an ADC are disclosed. In an embodiment, an analog-to-digital converter includes a DAC unit configured to convert a digital code to a first voltage in response to an input voltage of the ADC, a comparator configured to compare the first voltage with a second voltage to generate a comparison output, and a logic circuit configured to generate the digital code, to control the DAC unit based on the comparison output, and to output the digital code as a digital output of the ADC. The DAC unit includes a capacitive DAC and multiple resistive DACs. Each of the resistive DACs is connected to the first voltage through a respective capacitor.

Analog-to-digital converter, resistive digital-to-analog converter circuit, and method of operating an analog-to-digital converter

An integrated charge redistribution successive approximate register (CR-SAR) analog-to-digital converter (ADC) includes a sample-and-hold switch, a digital-to-analog converter (DAC), a comparator and a logic circuit. The sample-and-hold switch obtains a sample input voltage (Vin). The DAC includes a plurality of digital multiplexers that selects between a superposition phase, which superimposes an analog offset voltage onto Vin, and a conversion phase which determines values for a digital output register which determines the input values to each control line. Each digital multiplexer presents input values to a control line. The comparator has two inputs coupled to the sample-and-hold switch and to the DAC such that the output of the converter determines a value of each successive bit in the digital output register. The logic circuit is coupled to the comparator and to digital multiplexers and includes the digital output register.

Analog signal generation by hardware re-use in sampled circuits

A low dropout (LDO) regulator system is provided. The LDO regulator system includes a first amplifier circuit, a second amplifier circuit, and a switch circuit. The first amplifier circuit has a first input coupled to receive a reference voltage and an output. The second amplifier circuit has a first input coupled to the output of the first amplifier and is configured to provide a predetermined voltage at a first output. The switch circuit is coupled between the first output of the second amplifier circuit and a second input of the first amplifier circuit and is configured to cause an open circuit in a first feedback path from the first output of the second amplifier circuit to the second input of the first amplifier circuit based on a control signal.

Dual loop low dropout regulator system

The present application relates to an EQ circuit, a method of operating it and a system comprising the EQ circuit and an ADC. The EQ circuit has a configurable load section, which is provided for selectively exposing one of a plurality of distinct loads to a reference source connected to a reference voltage signal input of the equalization circuit, and a logic section, which is arranged to accept a state signal from the ADC and to selectively connect one distinct load out of the plurality of distinct loads in response to the state signal. The state signal is indicative of an actual operation state of the ADC.

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Zijtaart, Netherlands

Alphons Litjes