Psemi Corporation

Peregrine Semiconductor Corporation

Qualcomm Incorporated

Alper Genc

Christopher Nelles Brindle

Chieh-Kai Yang

Jie Deng

Ravindranath D Shrivastava

Mark L Burgener

Michael Andrew Stuber

George P Imthurn

David Francis Berdy

Peter Bacon

Dylan J Kelly

Eric S Shapiro

Robert Bernard Welstand

Clint L Kemerling

Jose Cabanillas

Fleming Lam

A (RF) switching system for minimizing received signal leakage during switching including a plurality of band filters comprising a first band filter, a second band filter, and a third band filter, first and a second antenna, and a switch configured to selectively couple the first, second and third filters to the first and second antennas and configured to receive complementary control signals, wherein at least the first and the second filter are configured to be simultaneously coupled to the first antenna and the switch is further configured to delay at least one of the complementary control signals when the switch, in response to the complementary control signals, is configured to selectively connect the first antenna to the third filter instead of the second filter while the first filter is coupled to the first antenna and a first communication path through the first filter to the first antenna is active.

System and method to reduce unwanted receive signal leakage during switching

Methods and devices to reduce gate induced drain leakage current in RF switch stacks are disclosed. The described devices utilize multiple discharge paths and/or less negative body bias voltages without compromising non-linear performance and power handling capability of power switches. Moreover, more compact bias voltage generation circuits with smaller footprint can be implemented as part of the disclosed devices.

Switch FET body current management devices and methods

A FET switch stack has a stacked arrangement of FET switches, a gate resistor network with ladder resistors and common gate resistors, and a gate resistor bypass arrangement. The bypass arrangement has a first set of bypass switches connected across the gate resistors and a second set of bypass switches connected across the ladder resistors. Bypass occurs during at least a portion of the transition state of the stacked arrangement of FET switches.

Gate resistive ladder bypass for RF FET switch stack

A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.

Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction

Methods and devices to reduce the gate-induced drain/body leakage current (GIDL) generated in FET switch stacks when in OFF state are disclosed. Such devices include inductors as part of bias networks coupled with drain/source terminals and/or body terminals of the transistors within the switch stack. Hybrid approaches where resistors in combination with inductors are implemented as part the bias network are also described.

Inductive drain and/or body ladders in RF switch stacks

Methods and devices to mitigate de-biasing caused by an undesired gate induced drain body leakage current in FET switch stacks are disclosed. The devices utilize diode stacks to generate discharge paths for the undesired current. The disclosed teachings are applicable to both shunt and series implementations of FET switch stacks.

Methods and devices to generate gate induced drain leakage current sink or source path for switch FETs

A common gate resistor bypass arrangement for a stacked arrangement of FET switches, the arrangement including a series combination of an nMOS transistor and a pMOS transistor connected across a common gate resistor. During at least a transition portion of the transition state of the stacked arrangement of FET switches, the nMOS transistor and the pMOS transistor are both in an ON state and bypass the common gate resistor. On the other hand, during at least a steady state portion of the ON steady state and the OFF steady state of the stacked arrangement of FET switches, one of the nMOS transistor and the pMOS transistor is in an OFF state and the other of the nMOS transistor and the pMOS transistor is in an ON state, thus not bypassing the common gate resistor.

Growing community of inventors

San Diego, CA, United States of America

Alper Genc