International Business Machines Corporation

Globalfoundries Inc.

University of Rochester

Globalfoundries U.S. 2 LLC

Alper Buyuktosunoglu

Pradip Bose

Augusto Javier Vega

Hans Mikael Jacobson

Karthik V Swaminathan

Philip George Emma

Michael B Healy

Vijayalakshmi Srinivasan

Bulent Abali

Allan Mark Hartstein

Krishnan Kunjunny Kailas

Tobias Webel

Brian Robert Prasky

Hubertus Franke

Phillip John Restle

Victor V Zyuban

Michael Stephen Floyd

Chen-Yong Cher

Preetham M Lobo

Timothy John Slegel

Richard Harold Boivie

Tong Chen

Jude A Rivers

Christos Vezyrtzis

Wei Zhang

Hillery C Hunter

John-David Wellman

Xiaodong Cui

Christian Jacobi

Prabhakar Nandavar Kudva

Swagath Venkataramani

Moinuddin K Qureshi

Deanna Postles Dunn Berger

Jeonghee Shin

Timothy Joseph Chainer

Toshiaki Kirihata

Anthony Saporito

Pritish Ranjan Parida

Ravi Nair

Martin Recktenwald

Giora Biran

Vaidyanathan Srinivasan

Rajiv V Joshi

Balaram Sinharoy

Eren Kursun

James J Bonanno

Richard James Eickemeyer

Stanley Everett Schuster

Brian William Curran

Gregory Scott Still

Todd Jon Rosedahl

Bruce Joseph Ronchetti

Peter William Cook

Bryan Savoye Rosenburg

Andrew A Turner

Robert Matthew Senger

Willm Hinrichs

Rajeev Balasubramonian

Michael K Gschwind

Chung-Lung K Shum

William John Starke

Dung Q Nguyen

Hung Qui Le

Robert K Montoye

Karthick Rajamani

Bartholomew Blaner

Michele M Franceschini

Cedric Lichtenau

Omer H Dokumaci

William Vincent Huott

Bruce Martin Fleischer

Jeffrey Haskell Derby

Susan Elizabeth Eisen

Lee Evan Eisen

Adam B Collura

Craig Raymond Walters

Thomas Winters Fox

Xiaoqiao Meng

Srinivasan Ramani

Canturk Isci

Xiaowei Shen

Emrah Acar

Yoonho Park

Mohit Karve

Michael J Cadigan, Jr

Benjamin P Segal

John Timothy Robinson

David Scott Ray

Seongwon Kim

Francis Patrick O'Connell

Miles Robert Dooley

Stefan Payer

Heather Lynn Hanson

Bishop Chapman Brock

Christopher J Gonzalez

Robert Alan Philhower

John Barry Griswell, Jr

Gero Dittmann

Timothy J Siegel

Raymond Cheung Yeung

Processing within a computing environment is facilitated by using cache hit-miss predictions. A cache hit-miss prediction is determined for a memory access instruction using a predictor. One or more speculative actions are controlled, based on determining the cache hit-miss prediction is a miss. The controlling is further based on a type of cache design.

Controlling speculative actions based on a hit/miss predictor

Examples described herein provide a computer-implemented method that includes generating an extended hot line table that tracks cross-core contended cache lines for multiple processors of a processing system based on cache requests, the extended hot line table storing at least metadata for a cross-core contended cache line. The method further includes polling, using firmware, the extended hot line table in each of the multiple processors of the processing system to identify contention information. The method further includes aggregating the contention information from each of the multiple processors to generate aggregated contention information. The method further includes processing subsequent cache requests using the aggregated contention information.

Detecting and mitigating false structure sharing within a cache line

Embodiments dynamically measure latency for a plurality of functions with a plurality of corresponding frequency levels within a serverless computing cluster; measure a transition latency from an idle state to an active state for the plurality of functions; determine whether a target response time to perform a service level objective (SLO) within the serverless computing cluster is going to be missed; dynamically reallocate at least one core and changing a frequency level across the plurality of functions by scaling down in response to a determination that the target response time to perform the SLO within the serverless computing cluster is going to be met; and dynamically reallocate the at least one core and changing the frequency level across the plurality of functions by scaling up in response to a determination that the target response time to perform the SLO within the serverless computing cluster is going to be missed.

Managing power for serverless computing

A cache hit-miss prediction is determined for a memory access instruction using a predictor. The predictor includes a tracker for the memory access instruction. The tracker is used to provide a prediction confidence level of the cache hit-miss prediction for the memory access instruction. Using the tracker, the prediction confidence level of the cache hit-miss prediction is ascertained. Based on the prediction confidence level indicating the cache hit-miss prediction is to be used, the cache hit-miss prediction is provided to be used in instruction execution scheduling.

Instruction execution scheduling using a hit/miss predictor

Embodiments for providing enhanced location-aware protection of latches in a computing environment are provided. One or more latches are combined in one or more of a plurality of bounding boxes on a two-dimensional circuit design layout based on one or more rules. A location-aware interleaving of error correction codes ('ECC') and burst error correction codes may be selectively applied to one or more latches in those of the plurality of bounding boxes, where multiple bit errors are corrected.

Location-aware protection system of latches (LAPS-L)

A method, system and apparatus for protecting a program from making out of bounds memory references, including determining whether an instruction makes out of bound references where the instruction that loads data from or stores data to a buffer refers to addresses that are outside the bounds of the buffer, and responsive to the determining that the instruction refers to addresses that are partially out of bounds, changing an execution of the load or the store including modifying the starting address specified in the instruction, a length of data specified in the instruction, or a value for an out of bounds reference to load or store data that is within the bounds of the buffer.

Safe execution of programs that make out-of-bounds references

Trustworthiness of an accelerator in heterogenous systems is increased. A workload of an application is offloaded to an accelerator for the accelerator to perform the workload. The accelerator is ensured to generate an output of the workload based on offloading the workload. The accelerator is identified as generating an output of the workload based on offloading the workload. Both an input and the output of the workload are ensured to be authentic based on offloading the workload to the accelerator. Both the input and the output of the workload are ensured to be securely transmitted based on offloading the workload to the accelerator.

Accelerator trustworthiness

In a first device, a local classification and a local classification confidence score corresponding to an event input are computed. At the first device in response to a broadcast request, a remote classification and a remote classification confidence score corresponding to the event input are received, the remote classification and the remote classification confidence score being computed at a second device. At the first device, a consensus classification including the most frequent classification from a set of all received remote classifications and the local classification is formed, provided the number of classifications including the most frequent classification exceeds a threshold. In response to a consensus classification confidence score corresponding to the consensus classification exceeding a confidence threshold, a local classification model is updated. Based on the local classification and the consensus classification, the event input is assigned to a classification.

Adaptive multi-agent cooperative computation and inference

A central processing unit (CPU) system including a CPU core can include an adaptive cache compressor, which is capable of monitoring a miss profile of a cache. The adaptive cache compressor can compare the miss profile to a miss threshold. Based on this comparison, the adaptive cache compressor can determine whether to enable compression of the cache.

Cache line compression prediction and adaptive compression

A computer-implemented method for detecting n-level slopes for a voltage level in a processor, wherein n is greater than 1, includes monitoring a voltage in a processor for a voltage level corresponding to a predefined first edge, and monitoring for a voltage level corresponding to a predefined second edge within a first count limit from detection of the predefined first edge. In response to detecting the predefined second edge within the first count limit, the computer-implemented method includes monitoring for a voltage level corresponding to a predefined third edge within a second count limit from detection of the predefined second edge, and in response to detecting the predefined third edge within the second count limit, determining whether to adjust a power applied to the processor based on the monitored voltage levels.

Voltage droop and overshoot management using non-linear slope detection

Embodiments include in response to monitoring a processor during operation, detecting a first number of throttling amounts in the processor, determining that the first number of throttling amounts fulfills a first condition regarding a throttling amounts threshold, and modifying a voltage level of the processor by a first amount. Embodiments include in response to modifying the voltage level of the processor by the first amount, detecting a second number of throttling amounts in the processor, determining that the second number of throttling amounts fulfills a second condition regarding the throttling amounts threshold, and modifying the voltage level of the processor by a second amount.

Dynamic guard band with timing protection and with performance protection

A method, system and apparatus for providing bound information accesses in buffer protection, including providing one-to-one mapping between a general-purpose register and bound information in a BI (bound information) register, saving loaded bound information in the BI register for future use, providing integrity of the bound information in the BI register that is maintained along program execution, and providing a pro-active load of the bound information with one-bit extra control on load instruction of the BI register.

Optimize bound information accesses in buffer protection

Embodiments of a method are disclosed. The method includes performing distributed deep learning training on multiple batches of training data using corresponding learners. Additionally, the method includes determining training times wherein the learners perform the distributed deep learning training on the batches of training data. The method also includes modifying a processing aspect of the straggler to reduce a future training time of the straggler for performing the distributed deep learning training on a new batch of training data in response to identifying a straggler of the learners by a centralized control.

Dynamic computation rates for distributed deep learning

A method, system and apparatus for protecting against out-of-bounds references, including storing an address of a buffer in a general register and storing bounds information (BI) for the buffer in a bounds information register, and when a content of the general register is used as an address in a load or store operation, using a content of the bounds information register to determine if the load or store is out of bounds.

Dedicated bound information register file for protecting against out-of-bounds memory references

Tasks of directed acyclic graphs (DAGs) may be dynamically scheduled based on a plurality of constraints and conditions, task prioritization policies, task execution estimates, and configurations of a heterogenous system. A machine learning component may be initialized to dynamically schedule the tasks of the DAGs.

Learning agent based application scheduling

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White Plains, NY, United States of America

Alper Buyuktosunoglu