Texas Instruments Corporation

Aloysious F Tasch, Jr

Pallab K Chatterjee

Perry A Penz

Hon W Lam

John M Pankratz

Method of fabricating a display with silicon integrated circuits included on the same monolithic structure and the flat panel display produced thereby. The display which may be of the liquid crystal or electrochromic type, for example, is formed as an x-y matrix display having individual address transistors respectively asociated with each of the display units or pixels. The substrate is preferably of transparent material, such as quartz or a glass plate, on which a polysilicon layer is disposed. The polysilicon layer is patterned to provide a plurality of islands which are subjected to a laser annealing treatment at an intensity sufficient to cause recrystallization thereof. The polysilicon material in the islands is converted by the laser annealing to crystalline silicon having an enhanced electron mobility characteristic such that a matrix array of address transistors in the form of MOSFETS can be fabricated in the individual islands. Thereafter, elements of the display are formed in conjunction with the matrix array of address transistors, beginning with the formation of an array of metal electrodes in respective association with corresponding address transistors. Various peripheral circuits for the display, such as drive circuits, are formed in other islands of crystalline silicon resulting from the laser annealing of the polysilicon islands such that a monolithic structure including a display with silicon integrated circuits for operating the display is produced.

Method of fabricating display with semiconductor circuits on monolithic

A charge coupled device is disclosed which includes a plurality of stages having increased charge storage capacity and decreased leakage current. Each stage is comprised of a semiconductor substrate of a first-type conductivity having a first surface. A charge transfer channel extends through the stage. An insulating layer of non-uniform thickness lies on the first surface. The insulating layer has at least two spaced apart relatively thick portions traversing the channel, and has relatively thin portions traversing the channel throughout the spaces between the spaced apart thick portions. Phase electrodes traverse the channel such that each phase electrode overlies one relatively thick portion and one adjacent relatively thin portion of the insulating layer. A shallow dopant layer of a second-type conductivity lies throughout the channel relatively near to the first surface. An enhanced first-type conductivity dopant layer lies throughout the channel relatively far from the first surface and has a doping which is greater than the doping of the first-type conductivity semiconductor substrate.

Non-coplanar barrier-type charge coupled device with enhanced storage

A charge coupled device is disclosed which includes a plurality of stages having increased charge storage capacity and decreased leakage current. Each stage is comprised of a semiconductor substrate of a first-type conductivity having a first surface. An insulating layer of uniform thickness lies on the first surface. A charge transfer channel extends through each stage. Phase electrodes lie on the insulating layer transversely to the channel. The semiconductor substrate under each phase electrode is divided into a barrier region and an adjacent well region bounded by the channel. A shallow dopant layer of the first-type conductivity lies in each of the barrier regions relatively near to the first surface. A buried channel dopant layer of a second-type conductivity lies in the well regions and the barrier regions under and relatively near to the shallow first-type conductivity dopant layer. Additionally, an enhanced first-type conductivity dopant layer lies in the well regions and the barrier regions under and relatively near to the buried channel dopant layer of second-type conductivity.

Co-planar barrier-type charge coupled device with enhanced storage

A charge coupled device memory is disclosed which includes a plurality of stages having increased charged storage capacity and decreased leakage current. Each stage is comprised of a semiconductor substrate of a first-type conductivity having a first surface. An insulating layer of uniform thickness lies on the first surface. A charge transfer channel extends through each stage. Phase electrodes lie on the insulating layer transversely to the channel. The semiconductor substrate under the phase electrodes is divided into barrier regions and adjacent well regions bounded by the channel. A dopant layer of a second-type conductivity lies in each of the well regions relatively near to the first surface. An enhanced first-type conductivity dopant layer lies in the well regions and the barrier regions relatively far from the surface having a doping which is greater than the doping of the first-type conductivity semiconductor substrate.

Co-planar well-type charge coupled device with enhanced storage capacity

Disclosed is a memory system capable of being integrated into a semiconductor substrate and having an array of Hi-C memory cells. The Hi-C cells are selectively addressable by row and column lines. Each cell of the array is comprised of a transistor having a source coupled to a bit line, a gate coupled to a word line, and a drain coupled to a node N. Node N is coupled in parallel to a dielectric capacitor and to a depletion capacitor. The dielectric capacitor and the depletion capacitor are constructed to have substantially the same charge capacity.

High capacity dynamic ram cell

Lithographic offset alignment techniques for MOS dynamic RAM memory cell fabrication to enable increased packing density while maintaining the minimum patterned geometry. Technique of cell fabrication involves initial oxidation of P-type silicon, for example, followed by silicon nitride deposition. Thereafter, moats are etched using the composite silicon dioxide-silicon nitride layers, followed by boron deposition or ion implantation in regions of the silicon substrate exposed by the etching treatment. The moats are then filled by oxidation to form a large field deposit of silicon dioxide extending above the level of the oxide layer in the regions where the moats were formed. The remaining composite silicon dioxide-silicon nitride layers are then removed, followed by gate oxidation. A P-type ion implant is provided beneath the thin oxide region between the regions to be overlaid by a polysilicon electrode and the thick field oxide of the succeeding cell. Thereafter, polysilicon is deposited and patterned, the patterned polysilicon electrode covering a fraction of the P-type implant. The gate oxide is then removed by etching, followed by N+ diffusion or ion implantation in the exposed region of the P-type implant to define a bit line having a length less than the minimum patterned geometry. Oxide is then applied by chemical vapor deposition, followed by a deposit of metal or polysilicon and patterning as required. The offset alignment of the polysilicon electrode with respect to the P-type implant creates the smaller dimension for the sense line. A fabrication technique for the CC RAM having an implanted storage region and a fabrication technique for a double-level polysilicon cell both using offset alignment techniques are also disclosed.

Growing community of inventors

Richardson, TX, United States of America

Aloysious F Tasch, Jr