Via Telecom Co., Ltd.

Via Telecom, Inc

Alon Saado

Qiang Shen

Muhammad Afsar

Linley Young

Tarun K Tandon

Kathy Lieberman

Victor Manzella

The invention relates to an internet application flow rate identification method based on message sampling and application signing, comprising the following steps: firstly, message sampling capture: in accordance with sampling strategy and sampling rate the message is captured and decoded; secondly, decoding: the flow information and application data of the message is analyzed by decoding the message; thirdly, flow classification: according to the flow information of the message, a flow state table is found and maintained; fourthly, flow state distinguishing: the signature is matched if the application type of the flow state found through the flow classification is unknown; finally, signature matching: according to the application signature bank, the application data of the message is matched, if matched successfully, the application type of the flow state is updated, and the flow information and application type of that data stream is output. The method is of high accuracy in identification, high efficiency in processing, good expandability, high possibility in realization, and is applicable not only for message processing, but also for flow data analysis. The invention can be achieved in not only the network equipment, but also the network analysis system.

Centralized recording and processing of received packet parameters

An apparatus comprising an address generation circuit, a lookup table, a multiplexer and an output circuit. The address generation circuit may be configured to generate a series of addresses. The lookup table may be configured to generate one or more coefficients in response to the addresses. The multiplexer circuit may be configured to generate one or more shifted values in response to (i) the coefficients and (ii) the one or more operands. The output circuit may be configured to generate an output signal by combining one or more component values in response to said shifted values. The coefficients are grouped as one over power of 2 components into mutually exclusive groups.

Canonical signed digit (CSD) coefficient multiplier with optimization

This invention discloses a system comprising a first comparator circuit configured to assert a first control signal in response to a first input number matching one of a first numbers stored therein, a second comparator circuit configured to assert a second control signal in response to: (i) at least one latched assertion of the first control signal; (ii) a second input number matching an intermediate number produced by incrementing the first input number; and (iii) an assertion of an input signal, and to de-assert the second control signal absent of either the matching between the second input number and the intermediate number or the de-assertion of the input signal, and a generator circuit configured to output a predetermined instruction data stored therein in response to the assertion of the first control signal, and to output a third number in response to the assertions of the second control signal.

Circuit and method for patching for program ROM

The present invention concerns an apparatus comprising a data unit, a memory and a control unit. The data unit may be configured to generate an output signal comprising a series of frames each having a header and a payload in response to an input signal comprising a series of words. The memory may be configured to hold the output signal and to interface with a device. The control unit may be configured to present one or more control signals configured to control the data unit and the memory.

Processing multiplex sublayer data unit data in hardware

A method and system is disclosed for generating one or more predetermined waveforms from one or more contiguous segments of at least one prototype waveform stored in one or more memory tables, the method and system comprising iterations of following sample processing steps: reading at least one sample of the stored prototype waveform at a predetermined address, modifying the sample according to a predetermined logic, and accumulating the modified sample, wherein through a predetermined number of iterations of above steps, a cycle of a new waveform is formed by the accumulated modified samples.

Waveform generation for FM synthesis

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a data output signal in response to a data input signal, a valid word signal, and a select signal. The second circuit may be configured to generate the select signal in response to the valid word signal, a start of frame signal, and end of frame signal and the data output signal. The select signal may adjust a starting point of each of the words to match a starting point of the first word.

Method and/or architecture implemented in hardware for the adjustment of messages with indeterministic length

The present invention concerns an apparatus comprising a logic circuit, a compare circuit, a control circuit and a memory interface. The logic circuit may be configured to generate a check signal in response to (i) a data signal having a series of logical transmission units (LTUs) and (ii) a first control signal. The compare circuit may be configured to generate a compare signal in response to the check signal and the data signal. The control circuit configured to generate (i) the first control signal and (ii) a second control signal indicating a valid or invalid status of each of the LTUs, in response to a data valid signal and the compare signal. The memory interface may be configured to generate an output data signal in response to the second control signal. The memory interface is generally configured to store only the LTUs having a valid status.

Method and/or apparatus implemented in hardware to discard bad logical transmission units (LTUs)

The present invention concerns an apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to read a data signal in response to a read enable signal. The second circuit may be configured to generate the read enable signal. The third circuit may be configured to present the data signal in response to a first state of the read enable signal and present a predetermined value in response to a second state of the read enable signal.

Read enable generator for a turbo decoder deinterleaved symbol memory

An apparatus comprising a circuit configured to be tested and a plurality of test blocks within the circuit. Each of the test blocks generally comprises (i) a plurality of sequential elements and (ii) a plurality of logic elements. Each of the test blocks are configured to operate (a) in a first mode comprising a shift mode and (b) a second mode comprising a capture mode. The shift mode generally operates with multiple scan clocks that are clocked simultaneously. The capture mode generally operates with multiple scan clocks, but only one of which is toggled at a time.

Method and/or apparatus for performing static timing analysis on a chip in scan mode with multiple scan clocks

A lock detector receives a feedback signal from a phase-locked loop and a reference signal. The lock detector includes a first generator for receiving the reference and feedback signals, and for sampling the feedback signal with the reference signal. A second generator is coupled to the first generator for incrementing a count when the feedback signal is at different polarities at consecutive edges of the reference signal. An output line, for asserting a phase lock when the count reaches a defined value, is coupled to the second generator.

Method and system for a lock detector for a phase-locked loop

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a gated clock signal in response to (i) a write enable signal and (ii) a system clock signal. The gated clock signal is pulsed active while the write enable signal is active. The second circuit may be configured to generate the write enable signal.

Method and/or apparatus for generating a write gated clock signal

The present invention concerns an apparatus comprising a memory, a logic circuit and a multiplexer. The memory generally comprises a first address space configured as read only and a second address space configured as read and write. The memory returns a first data item in response to a first address within the first address space. The logic circuit may be configured to (i) deassert a command signal in response to the first address not matching any of a plurality of predetermined addresses and (ii) generate a first branch instruction and assert the command signal in response to the first address matching one of the predetermined addresses in response to the matching. The multiplexer may be configured to select the first data item from the memory or the first branch instruction from the logic circuit in response to the command signal.

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San Diego, CA, United States of America

Alon Saado