Qualcomm Incorporated

Alon Naveh

Sagar Koorapati

Vinod Chamarty

Manu Gulati

Nitin Makhija

Anubhav Mishra

Gaurav Sanjeev Kirtane

Pushkin Raj Pari

Pradeep Kanapathipillai

Sreeram Jayadev

Broadcasting power limiting management responses in a processor-based system in an integrated circuit (IC) chip is disclosed herein. In one aspect, an IC chip comprises a processor-based system that includes a power estimation and limiting (PEL) circuit, a Limit Management Throughput Throttle (LMTT) source circuit, a plurality of activity management (AM) circuits, and an LMTT bus communicatively coupling the LMTT source circuit with each AM circuit of the plurality of AM circuits. The LMTT source circuit receives a power limiting management response from a PEL circuit via a communications network of the processor-based system, and generates an LMTT command based on the power limiting management response. The LMTT source circuit broadcasts the LMTT command to each AM circuit of the plurality of AM circuits via the LMTT bus.

Broadcasting power limiting management responses in a processor-based system in an integrated circuit (IC) chip

Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip, and related power management and power throttling methods are disclosed. The IC chip includes a processor as well as integrated supporting processing devices for the processor. The hierarchical power management system controls power consumption of devices in the IC chip to achieve the desired performance in the processor-based system based on activity power events generated from local activity monitoring of devices in the IC chip. To mitigate the delay in the reporting of activity power event of a monitored processing device that may affect throttling of power consumption for the IC chip, the power consumption of a monitored processing device can also be throttled locally throttle its power consumption. This gives reaction time for the power management system to receive and process activity power events to throttle power consumption in the IC chip.

Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip

Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip, and related power management and power throttling methods are disclosed. The IC chip includes a processor as well as integrated supporting processing devices for the processor. The hierarchical power management system controls power consumption of devices in the IC chip to achieve the desired performance in the processor-based system based on activity power events generated from local activity monitoring of devices in the IC chip. The circuit levels in the hierarchical power management systems are configured to be time synchronized with each other for the synchronized monitoring and reporting of activity samples and activity power events, and the generation of power limiting management responses to throttle power consumption in the IC chip.

Time synchronization of collecting and reporting power events between hierarchical power throttling circuits in a hierarchical power management system

Converting telemetry values into common data formats in a processor-based system in an integrated circuit (IC) chip is disclosed herein. In one aspect, an IC chip comprises a processor-based system that that is configured to receive an input telemetry value from an input source circuit. The processor-based system converts the input telemetry value into a common format telemetry value, wherein a first unit value represented by a least significant bit of the common format telemetry value is greater than one (1) and is based on a quotient of a power of two (2) and a corresponding power of 10. The processor-based system then processes common format telemetry value.

Converting telemetry values into common data formats in a processor-based system in an integrated circuit (IC) chip

A throttle control circuit receives a throttle control signal for controlling power consumption in a plurality of processing segment circuits. The throttle control signal has a throttle control value based on throttle requests from monitoring circuits that have detected power-related events or conditions and correspond to a requested change in activity in the plurality of processing segment circuits. The throttle control circuit receives the throttle control signal in a plurality of throttle administration circuits that each generates a throttle select signal to select an activity control signal for a corresponding processing segment circuit. In each of a first number (N) of consecutive cycles of a clock signal, the activity control signal disables state changes in the corresponding processing segment circuit for a second number (M) of cycles among the first number (N) of consecutive cycles to reduce power consumption in the processing segment circuits.

Throttle control circuits for throttling activity in processing segment circuits in an integrated circuit (IC) chip and related methods

This application is directed to power management at a processor system having a plurality of domains. Power samples are collected from the domains and combined to generate a system temperature profile including a temporal sequence of system temperature values. When the system temperature profile satisfies a first criterion, it is determined in real time whether a respective system temperature value of the system temperature profile satisfies a second criterion or a third criterion. In accordance with a determination that the respective system temperature value satisfies the second criterion, a power management engine determines power budgets of the domains on a firmware level and enables operations of the domains according to the power budgets. In accordance with a determination that the respective system temperature value satisfies the third criterion, a subset of domains are selected to apply a respective power throttling action directly on a hardware level.

Dynamic power management for SoC-based electronic devices

The processor-based system includes a throttle request accumulate circuit to receive throttle requests, determine a highest or most aggressive throttle value among the throttle requests, and generate a throttle control signal configured to throttle activity in the plurality of processing circuits. Throttle requests have throttle values corresponding to a reduction in activity in at least a portion of the plurality of processing circuits and may correspond to a particular number of cycles of reduced activity in a window of cycles. In addition to reducing response time to local events or conditions compared to waiting for a hierarchical response, the throttle request accumulate circuit accumulates throttle requests from all circuits that adjust or throttle activity in the plurality of processing circuits, and ensures that the net effective throttle controlling activity in the processing circuits at any given time is based on the highest throttle value of those accumulated throttle requests.

Integrated circuits (IC) chips including throttle request accumulate circuits for controlling power consumed in processing circuits and related methods

Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip, and related power management and power throttling methods are disclosed. The IC chip includes a processor as well integrated supporting processing devices for the processor. The hierarchical power management system controls power consumption of devices in the IC chip to achieve the desired performance in the processor-based system based on activity power events generated from local activity monitoring of devices in the IC chip. The hierarchical power management system includes a centralized power estimation and limiting (PEL) circuit that is configured to track and merge received power throttle recommendations associated with related activity power events for monitored processing devices to generate one or more power limiting management responses to throttle power consumption of related devices that may be contributing to excess power consumption.

Merging of power events related to estimated power consumption of different devices in a hierarchical power management system in an integrated circuit (IC) chip to perform power throttling

An electronic system has a plurality of power domains, and each domain includes a subset of one or more processor clusters, first memory, PMIC, and second memory. A plurality of power sensors are distributed on the electronic system and configured to collect a plurality of power samples from the power domains. A power management engine is configured to process the power samples based on locations of the corresponding power sensors to generate one or more power profiles and a plurality of power throttling thresholds. The power manage engine is configured to implement a global power control operation by determining power budgets of the power domains on a firmware level and enabling operations of the power domains accordingly. The power manage engine is also configured to enable a plurality of local power control operations to be directly implemented on the power domains based on the power throttling thresholds.

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Corte Madera, CA, United States of America

Alon Naveh