Intel Corporation

Alon Naveh

Eliezer Weissmann

Efraim Rotem

Doron Rajwan

Nadav Shulman

Avinash N Ananthakrishnan

Inder M Sodhi

Varghese George

Sanjeev S Jahagirdar

Stephen Anthony Fischer

Shai Rotem

David A Koufaty

Michael Mishaeli

Robert Milstrey

Boris Ginzburg

Dheeraj R Subbareddy

Eugene Gorbatov

Ganapati Srinivasa

Anil Aggarwal

Scott D Hahn

Paolo L Narvaez

Jason W Brandt

Krishnakanth Venkata Sistla

Stephen H Gunther

Hung-Piao Ma

Oren Lamdan

Mishali Naik

Andrew J Herdrich

Ronny Ronen

Eric C Samson

Nir Rosenzweig

Russell Jerome Fenger

Jorge Pedro Rodriguez

Gaurav Khanna

Ohad Falik

Ankush Varma

Jeremy J Shrall

Ryan Donovan Wells

Gary A Solomon

Andrew W Martwick

Ian M Steiner

Andrew D Henroid

Yuval Yosef

Edward R Stanford

Joseph T Dibene, Ii

Martin Rowland

Matthew M Bace

James B Crossland

Shivnandan D Kaushik

Douglas Raymond Moran

Roman Surgutchik

Kosta Luria

Bret L Toll

Hong Jiang

Ravishankar Iyer

Robert J Greiner

Ron Gabor

Keng L Wong

Vivek Garg

Jeffrey R Wilcox

Tsvika Kurts

Ashish V Choubal

Zeev Offen

Opher D Kahn

Shaun M Conrad

Michael Zelikson

John William Horigan

Hisham Abu Salah

Rakesh Kumar

Hisham Shafi

Rinat Rappoport

Abraham Mendelson

Nagabhushan Chitlur

Itamar S Kazachinsky

Mohan J Kumar

Stefan Rusu

David I Poisner

Ittai Anati

Koichi Yamada

Wei Ey Li

Ilan Pardo

Guy M Therien

Devadatta V Bodas

James G Hermerding, Ii

Robert E Gough

Bryant E Bigbee

Dan Baum

Sridhar Muthrasanallur

Michael N Derr

Konstantin Levit-Gurevich

Kushagra V Vaid

Lance E Hacking

Leslie E Cline

Justin J Song

Aamer Jaleel

Reid James Riedlinger

Ernest Knoll

Avi Mendelson

Tomer Ziv

Esfir Natanzon

Methods and apparatus relating to multi-level CPU (Central Processing Unit) high current protection are described. In one embodiment, different workloads may be assigned different license types and/or weights based on micro-architectural events (such as uop (micro-operation) types and sizes) and/or data types. Other embodiments are also disclosed and claimed.

Multi-level CPU high current protection

Embodiments of systems, apparatuses, and methods for energy efficiency and energy conservation including enabling autonomous hardware-based deep power down of devices are described. In one embodiment, a system includes a device, a static memory, and a power control unit coupled with the device and the static memory. The system further includes a deep power down logic of the power control unit to monitor a status of the device, and to transfer the device to a deep power down state when the device is idle. In the system, the device consumes less power when in the deep power down state than in the idle state.

Method, apparatus, and system for energy efficiency and energy conservation including autonomous hardware-based deep power down in devices

For one disclosed embodiment, a processor comprises a plurality of processor cores to operate at variable performance levels. One of the plurality of processor cores may operate at one time at a performance level different than a performance level at which another one of the plurality of processor cores may operate at the one time. The plurality of processor cores are in a same package. Logic of the processor is to set one or more operating parameters for one or more of the plurality of processor cores. Logic of the processor is to monitor activity of one or more of the plurality of processor cores. Logic of the processor is to constrain power of one or more of the plurality of processor cores based at least in part on the monitored activity. The logic to constrain power is to limit a frequency at which one or more of the plurality of processor cores may be set. Other embodiments are also disclosed.

Operating point management in multi-core architectures

Disclosed embodiments relate to processing logic for performing function operations. In one example, and apparatus includes an execution unit within a processor to execute a code block, power management hardware coupled to the execution unit, wherein the power management hardware is to monitor a first execution of the code block, store a micro-architectural context of the processor in a metadata block associated with the code block, the micro-architectural context including performance data resulting from the first execution of the code block, the performance data comprising power and energy usage data, and power management related parameters, read the associated metadata block upon a second execution of the code block, and tune the second execution based on the performance data stored in the associated metadata block to increase efficiency of executing the code block.

Mechanism for saving and retrieving micro-architecture context

In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

Dynamically controlling cache size to maximize energy efficiency

A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

Method for booting a heterogeneous system and presenting a symmetric core view

In one embodiment, a processor includes: a plurality of cores; a power controller including a logic to autonomously demote a first request for at least one core of the plurality of cores to enter a first low power state, to cause the at least one core to enter a second low power state, the first low power state a deeper low power state than the second low power state; and an interface to receive an input from a system software, the input including at least one demotion control parameter, where the logic is to autonomously demote the first request based at least in part on the at least one demotion control parameter. Other embodiments are described and claimed.

Providing an interface for demotion control information in a processor

In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.

User level control of power management policies

A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. Power management hardware during runtime monitors execution of a code block. The code block has been compiled to have a reserved space appended to one end of the code block. The reserved space includes a metadata block associated with the code block or an identifier of the metadata block. The hardware stores a micro-architectural context of the processor in the metadata block. The micro-architectural context includes performance data resulting from a first execution of the code block. The hardware reads the metadata block upon a second execution of the code block and tunes the second execution based on the performance data.

In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core. A task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS. Other embodiments are described and claimed.

Migrating tasks between asymmetric computing elements of a multi-core processor

A processor of an aspect includes at least one lower processing capability and lower power consumption physical compute element and at least one higher processing capability and higher power consumption physical compute element. Migration performance benefit evaluation logic is to evaluate a performance benefit of a migration of a workload from the at least one lower processing capability compute element to the at least one higher processing capability compute element, and to determine whether or not to allow the migration based on the evaluated performance benefit. Available energy and thermal budget evaluation logic is to evaluate available energy and thermal budgets and to determine to allow the migration if the migration fits within the available energy and thermal budgets. Workload migration logic is to perform the migration when allowed by both the migration performance benefit evaluation logic and the available energy and thermal budget evaluation logic.

Selective migration of workloads between heterogeneous compute elements based on evaluation of migration performance benefit and available energy and thermal budgets

Growing community of inventors

Ramat Hasharon, Israel

Alon Naveh