Intel Corporation

Alon Navch

Sanjeev S Jahagirdar

Stephen Anthony Fischer

Shai Rotem

Robert Milstrey

John B Conrad

George Varghese

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

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Ramat Hasharon, Israel

Alon Navch