International Business Machines Corporation

Intel Corporation

Alon Gluska

Dror Reif

Mostafa Hagog

Niraj Gupta

Laurent Fournier

Yossi Malka

Avi Ziv

Raanan Gewirtzman

Aharon Aharon

Yossi Lichtenstein

Schmuel Ur

Reuven Nisser

Flood-fill techniques and architecture are disclosed. In accordance with one embodiment, the architecture comprises a hardware primitive with a software interface which collectively allow for both data-based and task-based parallelism in executing a flood-fill process. The hardware primitive is defined to do the flood-fill function and is scalable and may be implemented with a bitwise definition that can be tuned to meet power/performance targets, in some embodiments. In executing a flood-fill operation, and in accordance with an example embodiment, the software interface produces parallel threads and issues them to processing elements, such that each of the threads can run independently until done. Each processing element in turn accesses a flood-fill hardware primitive, each of which is configured to flood a seed inside an N&#xd7;M image block. In some cases, processing element commands to the flood-fill hardware primitive(s) can be queued and acted upon pursuant to an arbitration scheme.

Parallel flood-fill techniques and architecture

Coverage measurement tool enabling a user to create a specific coverage tool for a coverage model including a set of coverage tasks specified by the user for checking a design such as a hardware or software system, and being associated with a database and model definition that defines the coverage model. The tool includes an insertion engine for storing into the database a table containing traces resulting from multiple tests, a processing engine processing the traces in the database according to the model definition, and a coverage analyzer analyzing the measurement results from the processing engine and preparing coverage analysis reports according to the model definition.

Coverage measurement tool for user defined coverage models

A technique that applies the task coverage exercised within a behavioral model of the design to the design itself, while simulating one or more test sequences. Since the behavior model is an accurate and complete program representation of the architectural specification of the hardware design, the test case coverage of the architecture is implied by the measurement of how well the behavioral model code has been exercised. The completeness of the coverage is determined by the test coverage criteria selected, including, for example, statement coverage, branch coverage, or path coverage. The more detailed the criteria, the greater the number of tests.

Method for measuring architectural test coverage for design verification

A method for the automatic verification of external interrupts in modern processor architectures under a very wide range of instruction sequences provides almost complete expected results from each of the involved interrupts. In particular, the method allows the verification of the architectural aspects to the external interrupt mechanism in pipelined and super scalar microprocessors. The method which is based on the assumption that when an external interrupt is serviced, the processor branches to a specific address according to the type of the external interrupt. The first step in the method is a preparation step wherein the memory addresses already used by the test are scanned and unused memory spaces are allocated for a plurality of memory blocks and two memory addresses for pointers. These two addresses are used to find the next block to fill. After this initial preparation step, the interrupt is presented in any desired location by the design simulator controller. Next, the instruction range in which the external interrupt could be serviced is found. External interrupt routines are added to the test. These routines are executed each time the appropriate external interrupt is served by the processor. Finally, the reference model of the processor is used to recompute the expected results of the test. In this process, each external interrupt will update its unique block of memory and, as a result, if the processor sets any of these resources to an incorrect value while servicing any of the external interrupts presented in the test, it will be detected as the actual results of the test will be different than those expected in the test program. A mask is used to detect latency violations. The value saved in memory is independent of the actual timing of the interrupt since all the unknown bits are reset by the mask. By using an offset, the chances of detection of a latency violation are improved.

Automatic verification of external interrupts

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Adi, Israel

Alon Gluska