Intel Corporation

Facebook Technologies, LLC

Meta Platforms Technologies, LLC

Alok Kumar Mathur

Shrirang Madhav Yardi

Drew Eric Wingard

Boris Beylin

Valerio Catalano

Wajdi K Feghali

Mark B Rosenbluth

Chee Hak Teh

Sridhar Lakshmanamurthy

Daniel Henry Morris

Jaroslaw Sydir

Sreenath Kurupati

Charles E Narad

Gang Lu

Steve John Clohset

Kamal J Koshy

Eduard Lecha

Hideo Tamama

Larry B Huston

Bijoy Bose

Irwin J Vaz

Ennio Salemi

Wujian Zhang

Weng Li Leow

Gregory L Limes

The disclosure describes artificial reality (AR) systems and techniques that enable hierarchical power management of multiple devices within a multi-device AR system. For example, a multi-device AR system includes a device comprising one of a peripheral device configured to generate artificial reality content for display or a head-mounted display unit (HMD) configured to output artificial reality content. The device comprises a System on a Chip (SoC) that includes a host subsystem and plurality of subsystems. Each subsystem includes a child energy processing unit configured to manage power states for the subsystem. The host subsystem includes a parent energy processing unit configured to direct power management of each of the child energy processing units of the plurality of subsystems.

Hierarchical power management in artificial reality systems

This disclosure describes various examples of a system which uses a multi-bank, multi-port shared memory system that may be implemented as part of a system on a chip. The shared memory system may have particular applicability in the context of an artificial reality system, and may be designed to have distributed or varied latency for one or more memory banks and/or one or more components or subsystems within the system on a chip. The described shared memory system may be logically a single entity, but physically may have multiple memory banks, each accessible by any of a number of components or subsystems. In some examples, the memory system may enable concurrent, common, and/or shared access to memory without requiring, in some situations, full locking or arbitration.

Artificial reality system having multi-bank, multi-port distributed shared memory

This disclosure describes techniques that include aligning processing of audio samples collected by multiple audio sensors or microphones. In one example, this disclosure describes a method comprising detecting a transition by the second microphone from a disabled state to an enabled state; after detecting the transition, performing phase alignment between audio samples collected by the first microphone and audio samples collected by the second microphone by introducing a delay in starting processing of the audio samples collected by the second microphone; and processing the phase-aligned audio samples.

Audio sample phase alignment in an artificial reality system

System on a Chip (SoC) integrated circuits are configured to reduce Static Random-Access Memory (SRAM) power leakage. For example, SoCs configured to reduce SRAM power leakage may form part of an artificial reality system including at least one head mounted display. Power switching logic on the SoC includes a first power gating transistor that supplies a first, higher voltage to an SRAM array when the SRAM array is in an active state, and a third power gating transistor that isolates a second power gating transistor from the first, higher voltage when the SRAM array is in the active state. The second power gating transistor further supplies a second, lower voltage to the SRAM array when the SRAM array is in a deep retention state, such that SRAM power leakage is reduced in the deep retention state.

Artificial reality system with reduced SRAM power leakage

This disclosure describes efficient communication of surface texture data between system on a chip (SOC) integrated circuits. An example system includes a first integrated circuit, and at least one second integrated circuit communicatively coupled to the first integrated circuit by a communication interface. The first integrated circuit, upon determining that surface texture data of a frame to be rendered for display by the second SoC integrated circuit is to be updated, (a) transmits the surface texture data in one or more update packets to the second integrated circuit using the communication interface, and (b) transmits a command to the second integrated circuit indicating that the surface texture data of the frame has been updated using the communication interface. The second integrated circuit, upon receipt of the command, (a) sets a pointer to a location in the display buffer storing the surface texture data of the frame, and (b) renders the surface texture data of the frame for display on a display device.

Artificial reality system using a multisurface display protocol to communicate surface data

In general, the disclosure describes techniques for wireless communications between multiple devices of an artificial reality system using virtual channels. In one example, a first computing device of a multi-device system, comprising: one or more first processors coupled to one or more memory devices; and a supervisory processor configured to establish a plurality of virtual channels over a physical wireless channel between the first computing device and a second computing device, wherein each of the virtual channels is associated with a different pair of processors comprising a source processor selected from one of the first processors or second processors of the second computing device and a destination processor selected from one of the first processors or the second processors, wherein, for each virtual channel and associated pair of processors, the source processor is configured to communicate application data with the destination processor using the virtual channel.

Artificial reality system with virtual wireless channels

This disclosure describes techniques that include aligning processing of audio samples collected by multiple audio sensors or microphones. In one example, this disclosure describes a method comprising enabling a first microphone; processing, by an audio processor and using a first processing pipeline, audio data samples collected by the first microphone; enabling a second microphone a period of time after enabling the first microphone; processing, by the audio processor and using a second processing pipeline, a sample of audio data collected by the second microphone by synchronizing starting times for the first and second processing pipelines.

Embodiments of techniques and systems for protected access to virtual memory are described. In embodiments, a protected memory management architecture ('PMMA') may be configured to control accesses to protected physical memory. The PMMA may provide a protected virtual memory window for dynamic allocation of protected memory regions. During forward translation of virtual memory addresses, the PMMA may check a region ID of a process before allowing access. During reverse translation of a physical memory address, the PMMA may prevent accesses to protected physical memory addresses. The PMMA may also dynamically allocate physical memory to protected memory regions in virtual memory and may authenticate the physical memory as available before allocation. Other embodiments may be described and claimed.

Protected access to virtual memory

A computer system may comprise a graphics controller, which may support a display handler. In one embodiment, the display handler may receive configuration values comprising a quantity value and a blending order. In one embodiment, the display handler may determine the number of universal pixel planes using the quantity value. The display handler may provide a number of universal pixel planes equal to the quantity value and the universal pixel planes may be provided using a reference universal pixel plane. The display handler may render each of the universal pixel planes into a type of pixel plane indicated by the corresponding elements of the blending order.

Processing pixel planes representing visual information

An embodiment of a system, method and apparatus is disclosed. The system comprises a first processor that is in communication with a root existence table. The first processor is to check the root existence table to determine if a character is a root character. A second processor is in communication with a root active list. The second processor is to retrieve an entry that corresponds to the character and to associate a pointer with the entry. A third processor is in communication with the second processor and a tree structure. The third processor is to receive the pointer from the second processor and to maintain the tree and table structure.

Full regular expression search of network traffic

A scalable, two-stage round-robin arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and an chassis interconnect that may be controlled to selectively connects a given master to a given target. The chassis interconnect includes multiple sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus. A two-stage arbitration scheme is employed to arbitrate access to the command bus. The first arbitration stage is used to arbitrate between command requests issued by masters in a given cluster. The second arbitration stage is used to arbitrate between winning first stage command requests. One embodiment of the arbitration scheme employs re-circulation of second stage losers. Another embodiment employs re-prioritization of second stage losers.

Scalable, two-stage round robin arbiter with re-circulation and bounded latency

Configurable CRC calculation engines and methods of performing CRC calculations are presented. The configurable CRC calculation engines calculate a CRC value for the data using an associated polynomial and remainder. The method includes receiving a polynomial, receiving a block of data to determine a CRC value for, and calculating a CRC value for the data using the polynomial. With such devices and methods, the configurable CRC calculation engines are useful in various applications and protocols.

Growing community of inventors

Cupertino, CA, United States of America

Alok Kumar Mathur