Xilinx, Inc.

Synopsys, Inc.

Synopsis Incorporated

Alok Kuchlous

Sridhar Subramanian

Sridhar Narayanan

Chaiyasit Manovit

Guillermo R Maturana

Wanlin Cao

Arnob Roy

Sanjay Malpani

One embodiment of a method for verifying functional equivalency between a design of an integrated circuit and a corresponding clock-gated design utilizing output-based clock gating includes selecting a first one of a first plurality of internal state elements in the design and a corresponding first one of a second plurality of internal state elements in the clock-gated design, wherein an input to the first one of the first plurality of internal state elements serves as a first comparison point and an input to the corresponding first one of the second plurality of internal state elements serves as a second comparison point, and the design is to be compared against the clock-gated design at the first comparison point and the second comparison point and generating a test bench that identifies the first comparison point and the second comparison point as a set of comparison points.

Method and apparatus for verifying output-based clock gating

One embodiment of the invention provides a system that facilitates integrating a simulation log into a verification environment. The system operates by first creating the simulation log during a simulation of a register transfer language description of an integrated circuit design. Next, for each entry in the simulation log, the system places a corresponding entry in a 'log entry table.' When a user selects an entry from the simulation log, the system determines a file offset for the entry within the simulation log. Next, the system locates the corresponding entry in the log entry table. The system then uses the log entry table to locate entries within simulator state files, which describe which portion of the integrated circuit is being simulated. This enables the system to display the corresponding entries from the simulator state files to a user.

Method and apparatus for integrating a simulation log into a verification environment

A simulation architecture and method having four major steps. Firstly, an input circuit description to be simulated is compiled into an initial circuit compilation as follows. The input circuit description is translated into an initial register transfer level (RTL) network representation comprised of sequential and/or combinational objects. Next, translation of the RTL network into a network of clusters is accomplished. In general, a cluster is a region of the circuit which has uniform simulation activity. The initial clustering process, by default, chooses an simulation mode for all clusters known as event-triggered cycle-based. The other possible simulation mode for a cluster, in accordance with the present invention, is oblivious-triggered cycle-based. The first major step completes with translating the network of clusters into simulatable object code which includes additional object code that generates activity data regarding each cluster during a simulation. In the second major step, part of the complete suite of test vectors, such portion being known as profile test vector subset, is simulated upon the object code of the initial circuit compilation to produce activity data. For the third major step the input circuit description to be simulated is compiled again, but is optimized utilizing the activity data. The activity data is used to decide which clusters should either be merged into larger event-triggered cycle-based clusters or individually switched from event-triggered cycle-based simulation to oblivious-triggered cycle-based simulation. The simulation mode is chosen, or clusters are merged, on a cluster-by-cluster basis, to optimize simulation efficiency (and therefore minimize simulation time). Finally, in the fourth major step the optimized circuit compilation is simulated with the full suite of test vectors.

Method and apparatus for adaptively or selectively choosing event-triggered cycle-based simulation or oblivious-triggered cycle-based simulation on a cluster-by-cluster basis

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Bengaluru, India

Alok Kuchlous