Applied Materials, Inc.

Alok Jain

Wei Liu

Deenesh Padhi

Xinhai Han

David S Mui

Dragan Valentin Podlesnik

Nagarajan Rajagopalan

Hang Yu

Masaki Ogata

Bikram Kapoor

Yoshio Ishikawa

Wenjiao Wang

Kristopher R Enslow

Chuanxi Yang

Chuan Ying Wang

Joshua Maher

Farhan Ahmad

Kesong Hu

SeoYoung Lee

Michael Awdshiew

Michelle Siew Mooi Low

Gang Zou

Hiroya Tanaka

Chee Khiang Ivan Sim

Phaik Lynn Leong

Grace Qi En Teong

Phui Fah Chong

Exemplary methods of forming semiconductor structures may include forming a silicon oxide layer from a silicon-containing precursor and an oxygen-containing precursor. The methods may include forming a silicon nitride layer from a silicon-containing precursor, a nitrogen-containing precursor, and an oxygen-containing precursor. The silicon nitride layer may be characterized by an oxygen concentration greater than or about 5 at. %. The methods may also include repeating the forming a silicon oxide layer and the forming a silicon nitride layer to produce a stack of alternating layers of silicon oxide and silicon nitride.

Modified stacks for 3D NAND

A dual damascene trench etching process includes a two-step BARC etching process, a first BARC etch step using a fluorocarbon-based plasma, and a second BARC etch step using an O/N-based plasma. The first BARC etch step removes a first portion of the BARC covering a dielectric stack using a fluorocarbon-based plasma. The second BARC etch step removes a second portion of the BARC covering the dielectric stack using a O/Nbased plasma. The dual damascene trench etching process may further include a BARC etch back process to remove a further portion of the BARC not covering the dielectric stack. The dual damascene trench etching process further includes a low-k dielectric etching process that etches trenches in a low-k dielectric layer in the dielectric stack and that avoids the use of argon in order to prevent facet formation.

Dual damascene etch processes

The present invention provides a low-k dielectric etching process with high etching selectivities with respect to adjacent layers of other materials, such as an overlying photoresist mask and an underlying barrier/liner layer. The process comprises the step of exposing a portion of the low-k dielectric layer to a plasma of a process gas that includes a fluorocarbon gas having a relatively low fluorine to carbon ratio, a nitrogen-containing gas, and an inert gas, wherein a volumetric flow ratio of the nitrogen-containing gas to the fluorocarbon gas is greater than about 20:1. The process can be used to over etch the low-k dielectric layer to provide improved selectivity to the photoresist mask and the barrier/liner layer, reduced striations and reduced CD loss as compared with conventional low-k dielectric etching processes.

Selective etching of low-k dielectrics

A method of depositing a film on a substrate. In one embodiment, the method includes depositing a first portion of the film using a high density plasma to partially fill a gap formed between adjacent features formed on the substrate. The film deposition process is then stopped before or shortly after the entry of the gap pinches off and the film is etched to widen entry to the gap using a two step etching process that includes a first physical etch step that forms a plasma from a sputtering agent introduced into the processing chamber and biases the plasma towards the substrate and a subsequent chemical etch step that forms a plasma from a reactive etchant gas introduced into the processing chamber. After the etching sequence is complete, a second portion of the film is deposited over the first portion using a high density plasma to further fill the gap.

High density plasma CVD process for gapfill into high aspect ratio features

The present disclosure includes a method of plasma etching a trench having rounded top corners in a silicon substrate. One embodiment includes the following general steps: a) providing a semiconductor structure comprising a hard masking layer, overlying a silicon substrate; b) plasma etching through said hard masking layer and any additional underlying layers overlying said silicon substrate using at least one plasma feed gas which does not provide polymer deposition on surfaces of said semiconductor structure during etching; where said plasma etching exposes a face of said silicon substrate; and c) plasma etching at least a first portion of a trench into said silicon substrate using reactive species generated from a feed gas comprising a source of fluorine, a source of carbon, a source of hydrogen, and a source of high energy species which provide physical bombardment of said silicon substrate. Top corner rounding is effected by deposition of a thin layer of polymer on a top corner of the trench during etching of the first portion of the trench, resulting in the formation of a rounded &ldquo;shoulder&rdquo; at the top corner of the trench. Typically a layer of silicon oxide overlies at least a portion of the silicon substrate surface. The method described provides excellent critical dimension control over the active area of a transistor produced using the method and reduces the need to remove polymer from substrate and reactor surfaces after etching of the silicon trench.

Method for etching a trench having rounded top corners in a silicon substrate

Growing community of inventors

Singapore, Singapore

Alok Jain