Cadence Design Systems, Inc.

Alok Jain

Manu Chopra

Pradeep Goyal

Kavita Ravi

Robert Paul Kurshan

Ravi Prakash

Xiaoqun Du

Erich Marschner

Vinaya Kumar Singh

Sandeep Pagey

Ronald H Hardin

Yaron Peri-Glass

Axel Siegfried Scherer

Franz Erich Marschner

Frank Armbruster

Dan Leibovich

Swapnajit Chakraborti

Pratik Mahajan

Deepak Yadav

Manpreet Singh Reehal

Anurag Gupta

F Erich Marschner

The present disclosure relates to a method for formal verification of an integrated circuit design. The method may include providing an electronic design associated with the integrated circuit. The method may further include generating one or more faults in a cone of influence of an assertion and placing a constraint configured to model an original design for the one or more faults. The method may also include initiating formal verification on the electronic design while ignoring all electronic design constraints. The method may further include determining if the assertion is passing, wherein determining includes activating an original design for a subset of faults. If the assertion is passing, the method may include activating a single fault from the subset, determining if the assertion is passing and if the assertion does pass, deleting the single fault from the subset.

Method for mutation coverage during formal verification

The present disclosure relates to a method for debugging in the formal verification of an integrated circuit design. The method may include providing, via a computing device, an electronic design associated with the integrated circuit. Embodiments may further include splitting one or more nets in a cone of influence of a target associated with the electronic design. For each split net, embodiments may include placing a constraint that re-joins the net. Embodiments may also include identifying a local region of the electronic design for which the target is unreachable. During formal verification, embodiments may include ignoring all constraints associated with the local region of the electronic design.

Method for debugging unreachable design targets detected by formal verification

A method and apparatus for producing a vacuity detection report to reduce false positive verification results for digital circuits provided. In an exemplary embodiment, a design description of the digital design is generated. From the design description, a vacuity detection problem is derived by introducing an assertion into the design description. By introducing an assertion into the design description, the vacuity detection problem is solvable by formal assertion based verification engines. A verification engine is then used to solve the vacuity detection problem and produce a vacuity detection report. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the subject matter of the disclosure contained herein. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.

System method and apparatus for vacuity detection

A method and apparatus for producing a verification of digital circuits are provided. In an exemplary embodiment on the invention, a plurality of verification scopes of an integrated circuit design as defined as part of a verification plan. A plurality of verification runs are executed within two or more verification scopes defined by the verification plan. At least two verification runs are selected to merge verification results together. Like named scenarios are merged together for each verification scope to generate merged verification results that are then stored into a merge database. A verification report is generated for the integrated circuit design from the merged verification results. A merge point may be specified so like named subtrees and subgroups may be merged across different verification scopes of selected verification runs. The merge point may combine check and coverage results obtained during simulation with check and coverage results obtained during formal verification.

Verification plans to merging design verification metrics

The present disclosure relates to a method for minimizing constraints in the formal verification of an integrated circuit design. The method may include obtaining an unisolated list of constraints initially comprising all known constraints for the integrated circuit design and obtaining an isolated list of constraints initially comprising none of the known constraints. The method may further include attempting to prove an assertion without the known constraints and determining if the assertion is valid. The method may further include updating the isolated list of constraints.

Constraint minimization method for formal verification

Verification model of static state retention behavior of a state saving element design during power shut off of the state saving element in an integrated circuit design including: creating in a computer readable medium a model of a single edge triggered state saving element; and creating in the computer readable medium clock gate logic that suspends saving of new states by the single state saving element upon the occurrence of a first state retention signal in preparation for power shut off.

State retention for formal verification

A method and system for verifying circuit designs through propagation of assertions within a circuit design. In an embodiment, a plurality of provided assertions a circuit design are propagated within the circuit design. The circuit design is then verified using at least one of the propagated assertions as an assumption.

Method and system for verifying circuit designs through propagation of assertions

Aspects of computing design invariants, by using approximate reachability analysis, include reducing the circuit model for verification and synthesis. Further included is computing invariants using approximate reachability analysis to optimize a circuit model by identifying a plurality of next states for a present state, the plurality of next states capable of being reached from the present state in one transition. The plurality of bits of the next states are compared with a plurality of bits of the present state, and each bit of the present state that is different from at least one next state is changed to variant.

Design optimization using approximate reachability analysis

A method and system for verifying integrated circuit designs through partitioning. In an embodiment, a design is partitioned, then each partition is verified. In one embodiment, the design is partitioned at the granularity of modules. In another embodiment, the design is partitioned at the granularity of instances. In a third embodiment, instances are grouped together, subject to a weight threshold, so as to form possibly overlapping partitions of instances that are contiguous in the design hierarchy, with the purpose of avoiding, to the extent possible, false negatives. In a further embodiment, the design is partitioned to avoid redundant partitions. In an embodiment, model checking is applied to one or more local properties in each partition. In another embodiment, simulation is used to verify each partition.

Method and system for partitioning an integrated circuit design

A mechanism is disclosed for recognizing and functionally abstracting a column of memory cells. According to one embodiment, a column of n (where n is an integer greater than 1) memory cells is identified in a description of a circuit. One of the n memory cells is selected as a representative memory cell. Then, the column of n memory cells is represented as a single-memory-cell column comprising the representative memory cell. The column is thereafter functionally abstracted to derive a logic-level representation of the memory cell. After that is done, n&#x2212;1 additional instances of the logic-level representation are generated. In this manner, the column of n memory cells is functionally abstracted as a column of n logic-level representations of the representative memory cell.

Mechanism for recognizing and abstracting memory structures

An abstraction mechanism is disclosed, which is capable of recognizing and abstracting precharged latches and flip-flops, and which is capable of generating a cycle ready representation of the precharged latches and flip-flops. In one embodiment, the abstraction mechanism abstracts precharged latches and flip-flops by using cofactors. In doing so, the abstraction mechanism accesses a logic level representation of a structure. Based upon the logic level representation, the abstraction mechanism derives one or more cofactors. These cofactors are then tested to determine whether they indicate precharge behavior, and whether they indicate latch or flip-flop behavior. If the cofactors indicate both precharge behavior and latch or flip-flop behavior, then the abstraction mechanism abstracts the structure as a precharged latch, or a precharged flip-flop, whichever is appropriate. By recognizing and abstracting precharged latches and flip-flops in this manner, the abstraction mechanism simplifies the functional representation of the structure, and makes it possible to generate a cycle ready representation of the structure.

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New Delhi, India

Alok Jain