Allos Semiconductors Gmbh

Azur Space Solar Power Gmbh

Aixtron Ag

Azzuro Semiconductors Ag

Laytec Gmbh

Azzurro Semiconductors Ag

Alois Krost

Armin Dadgar

Holger Jurgensen

Holger Jürgensen

Thomas Zettler

Fabian Schulze

Guenther Strassburger

A process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising: provision of a substrate having a silicon surface; deposition of an aluminium-containing nitride nucleation layer on the silicon surface of the substrate; optional: deposition of an aluminium-containing nitride buffer layer on the nitride nucleation layer; deposition of a masking layer on the nitride nucleation layer or, if present, on the first nitride buffer layer; deposition of a gallium-containing first nitride semiconductor layer on the masking layer, wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 μmin a layer plane of the coalesced nitride semiconductor layer that is perpendicular to the growth direction.

Nitride semiconductor component and process for its production

A process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising:

Group III nitride layers have a wide range of uses in electronics and optoelectronics. Such layers are generally grown on substrates such as sapphire, SiC and recently Si(111). For the purpose inter alia of integration with Si-CMOS electronics, growth on Si(001) is indicated, which is possible only with difficulty because of the different symmetries and is currently limited solely to misoriented Si(001) substrates, which restricts the range of use. In addition, the layer quality is not at present equal to that produced on Si(111) material. Growth on exactly oriented Si(001) and an improvement in material quality can now be simply achieved by a modification of the surface structure possible with a plurality of methods.

Epitaxial group III nitride layer on (001)-oriented group IV semiconductor

The invention relates to a device and a method for the measurement of the curvature of a surface (), which is more exact and less expensive than prior art devices. The device comprises a light source () for the irradiation of a light beam () onto the surface (), in which a birefingent element () is arranged between light source () and surface (), in which furthermore a detector () is arranged for the detection of the partial beams (), that are reflected from the surface (), and at least one main axis () of the birefringent element () is positioned with respect to the light beam () of the light source () in such a way, that the light beam () of the light source () is split up into at least two parallel beams ().

Device and method for the measurement of the curvature of a surface

This invention relates to a method for depositing III-V semiconductor layers on a non III-V substrate especially a sapphire, silicon or silicon oxide substrate, or another substrate containing silicon. According to said method, a III-V layer, especially a buffer layer, is deposited on the substrate or on a III-V germination layer, in a process chamber of a reactor containing gaseous starting materials. In order to reduce the defect density of the overgrowth, a masking layer consisting of essentially amorphous material is deposited directly on the III-V germination layer or directly on the substrate, said masking layer partially covering of approximately partially covering the germination layer. The masking layer can be a quasi-monolayer and can consist of various materials.

Process for depositing III-V semiconductor layers on a non-III-V substrate

The invention relates to a method for depositing thick III-V semiconductor layers on a non-III-V substrate, particularly a silicon substrate, by introducing gaseous starting materials into the process chamber of a reactor. The aim of the invention is to carry out the crystalline deposition of thick III-V semiconductor layers on a silicon substrate without the occurrence of unfavorable lattice distortions. To this end, the invention provides that a thin intermediate layer is deposited at a reduced growth temperature between two III-V layers.

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Berlin, Germany

Alois Krost