Infineon Technologies Ag

International Business Machines Corporation

Samsung Electronics Co., Ltd.

Chartered Semiconductor Manufacturing Ltd (corporation)

Other

Infineon Technologies North America Corp.

Infineon North

Alois Gutmann

Chandrasekhar Sarma

Sajan Marokkey

Jiang Yan

Jin-Ping Han

Jingyu Lian

Roland Hampp

Haoren Zhuang

Matthias Lipinski

Hermann Wendt

Henning Haffner

Markus Naujok

Muhammed Shafi Pallachalil

Zhijian Lu

Josef Maynollo

Scott Jansen

Danny Pak-Chum Shum

Chun-Yung Sung

Manfred Eller

Yung Fu Chong

Sung-Chul Park

Roman Knoefler

O Sung Kwon

Alan C Thomas

Fang Chen

Chris Stapelmann

Bruno Spuler

Byung-Goo Jeon

Nikki Edleman

Gary Williams

Margaret C Lawson

Kuang Jung Chen

Sunfei Fang

Uwe Paul Schroeder

Gerhard Kunkel

Shahid Ahmad Butt

Johnny Widodo

Ja-Hum Ku

Shoaib Hasan Zaidi

Len Yuan Tsou

Helen Wang

Klaus Herold

Chong Kwang Chang

Jae-eon Park

Roderick Koehle

Gabriela Brase

Jun-jung Kim

Syed Shoaib Hasan Zaidi

O-sung Kwon

Dae-won Yang

Mike Armacost

Alan Thomas

Margaret Lawson

A structure having air gaps between interconnects is disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.

Semiconductor devices and structures thereof

Stress-inducing structures, methods, and materials are disclosed. In one embodiment, an isolation region includes an insulating material in a lower portion of a trench formed in a workpiece and a stress-inducing material disposed in a top portion of the trench over the insulating material.

Stress-inducing structures, methods, and materials

Multi-beam lithography systems and methods of manufacturing semiconductor devices using the same are disclosed. For example, the method utilizes non-coincidence of boundaries of electrical fields emanating from chrome on glass or phase shifted mask features distributed over two masks for the optimization of lithographic process windows, side lobe suppression, or pattern orientation dependent process window optimization employing one mask with polarization rotating film on the backside.

Lithography systems and methods of manufacturing using thereof

Methods for manufacturing semiconductor devices are disclosed. One preferred embodiment is a method of processing a semiconductor device. The method includes providing a workpiece having a material layer to be patterned disposed thereon. A masking material is formed over the material layer of the workpiece. The masking material includes a lower portion and an upper portion disposed over the lower portion. The upper portion of the masking material is patterned with a first pattern. A polymer material is disposed over the masking material. The masking material and the polymer layer are used to pattern the material layer of the workpiece.

Semiconductor device manufacturing methods

Mark and method for integrated circuit fabrication with polarized light lithography. A preferred embodiment comprises a first plurality of elements comprised of a first component type, wherein the first component type has a first polarization, and a second plurality of elements comprised of a second component type, wherein the second component type has a second polarization, wherein the first polarization and the second polarization are orthogonal, wherein adjacent elements are of different component types. The alignment marks can be used in an intensity based or a diffraction based alignment process.

Alignment marks for polarized light lithography and method for use thereof

Semiconductor devices and methods of manufacturing thereof are disclosed. A plurality of features is formed on a workpiece, the plurality of features being located in a first region and a second region of the workpiece. Features in the first region have a first lateral dimension, and features in the second region have a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension. The first region is masked, and the second lateral dimension of features in the second region is reduced.

Semiconductor devices and methods of manufacturing thereof

A method for forming a contact hole in a semiconductor device and related computer-readable storage medium are provided, the method and program steps of the medium including measuring a percentage of oxygen in an etching chamber, and controlling the percentage of oxygen in the etching chamber to enlarge a temporary inner diameter near a top of the contact hole.

Contact patterning method with transition etch feedback

Methods of forming air gaps between interconnects of integrated circuits and structures thereof are disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.

Methods of manufacturing semiconductor devices

In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.

Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same

Lithography masks and methods of manufacture thereof are disclosed. For example, a method of manufacturing a lithography mask includes forming a stack over a substrate. The stack includes bottom attenuated phase shift material layers, intermediate opaque material layers, and finally top resist layers. The method further includes patterning the stack and then trimming the resist layers to uncover a portion of the opaque material layers. The uncovered opaque material layers are subsequently etched followed by removal of any remaining resist layers.

Lithography masks and methods of manufacture thereof

Growing community of inventors

Poughkeepsie, NY, United States of America

Alois Gutmann