Nxp B.v.

Nxp Usa, Inc.

Alma Anderson

Amrita Deshpande

Jean-Marc Irazabal

Stephen Blozis

Paul Boogaards

Joseph Dale Rutkowski

Jay Richard Lory

Dave Oehler

Gijs Jan De Raad

Brad Gunter

James Caravella

Hok-tung Wong

Manoj Chandran

Yang Zhao

An ESD circuit includes an ESD clamp device with an ESD clamp transistor. The ESD clamp transistor has two sets of one or more body contacts. One set is coupled to a supply voltage rail and the other set is coupled to a clamp activation circuit. The clamp activation circuit is coupled to a clamp device. During an electrical stress event of a sufficient severity affecting a supply voltage rail, the activation circuit makes the clamp device conductive to transfer charge between supply voltage rails.

Clamp device activation from ESD clamp transistor body contact

Embodiments of input supply circuits and methods for operating an input supply circuit are described. In one embodiment, an input supply circuit includes a bias circuit configured to define a voltage threshold in response to an input signal, and an input buffer configured to generate an output signal in response to the voltage threshold. Other embodiments are also described.

Input supply circuit and method for operating an input supply circuit

Embodiments of an electrostatic discharge (ESD) protection device and a method for operating an ESD protection device are described. In one embodiment, an ESD protection device includes a primary ESD protection unit electrically connected to a first node and to a second node and configured to shunt current in response to an ESD pulse received between the first and second nodes and a secondary ESD protection unit electrically connected to the primary ESD protection unit and to the second node and configured to shunt current in response to the ESD pulse to keep an output voltage of the ESD protection device to be within a safe operating voltage range of a device to be protected. Other embodiments are also described.

Device and method for electrostatic discharge (ESD) protection

A reference output device includes a low side selector configured to select a first voltage level as an output signal. The output signal is a reference voltage. The reference output device also includes a high side selector configured to select a second voltage level as the output signal. The reference output device also includes a slew rate control configured to switch the output signal between the first voltage level and the second voltage level at a constant slew rate.

Slew rate control for multiple voltage domains

Aspects of the present disclosure are directed towards apparatus useful for processing communications between different signaling voltage levels. Different signaling voltage levels are accomplished by creating true and complement signals from at least one input signal, each of which are subject to different delays, and level shifting the true and complement signals to a new signaling voltage level. The true or complement signal subject to a smaller timing delay is selected, and used to provide an output signal.

Asymmetric propagation delays in level shifters and related circuits

A system and method for synchronizing otherwise independent oscillators private to IC Bus slave devices. An IC Bus master device can issue two new general call commands, CALIBRATE and ZERO COUNTERS. The IC Bus slave devices respond to the CALIBRATE command by counting the number of cycles its local, private oscillator makes through during the communication transfer period of the CALIBRATE command on the IC Bus. All such IC Bus slave devices measure the same communication transfer period on the IC Bus, so the differences in the digital measurements obtained by each of them are proportional to their respective oscillator frequencies. The digital measurements are privately used by each IC Bus slave device to calculate appropriate oscillator prescale factors, and to automatically load the values that will harmonize the final product frequencies of all of the local oscillators on all of the IC Bus slave devices in the system.

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An edge rate suppression circuit arrangement is provided for operation with an open drain bus. The circuit arrangement includes a variable resistive circuit having an input for receiving a variable voltage signal and an output coupled to the open drain bus, and a control circuit configured to operate the variable resistive circuit. The control circuit operates the variable resistive circuit in respective high and low resistance states in response to the variable voltage signal.

Edge rate suppression for open drain buses

Methods and apparatus for implementing and operating pulse width modulation based LED dimmer controllers are described. A synchronization protocol is used to allow control information for the dimmer operations to be transferred to the PWM dimmer control clock domain from an external clock domain, such that visual artifacts are prevented when the control information is updated. Control information may be transferred to the LED dimmer controller via an I2C serial bus, and the synchronization protocol waits for an I2C STOP condition before updating control information across clock domain boundaries. The leading and trailing edges of an asserted group dimmer control signal are generated such that the active portion of the group dimmer control signal overlaps the active portion of individual LED pulse width modulated control signals. In this way, the pulse width modulation of the individual LED control signals is not cut off, or reduced in width by the group dimmer signal.

Pulse width modulation based LED dimmer control

Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate programming of parallel slave devices concurrently using an I2C serial bus. At least two slave devices are coupled in parallel on the data transfer bus and configured to load serial data over the serial data line using the communications protocol. Each slave device includes a programmable configuration register configured to be programmed, using the communications protocol, to select one of a plurality of selectable slave device configurations. One of the selectable slave device configurations causes the at least two slave devices to load the serial data in parallel, and another of the selectable slave device configurations causes the at least two slave devices to be loaded one at a time.

Programming parallel I2C slave devices from a single I2C data stream

Consistent with an example embodiment, an edge-rate control circuit arrangement () for an I2C bus application comprises a first circuit stage (, M, M), responsive to a state transition of a received signal. A second circuit stage (, M, ESD) is responsive to the state transition of the received signal and includes drive circuitry (M) that is activated in response to the state transition of the received signal in order to provide an edge-transition signal for an I2C bus, and regulation circuitry (, R, R, M, M) adapted to control the drive circuit and regulate a transition rate for the edge-transition signal, the transition rate being greater than a transition rate of the received signal at the first circuit stage and greater than a minimum and less than a maximum transition rate designated for communication on the I2C bus.

Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate programmable loading of a logic value into parallel slave device registers. The communications system includes a slave device having two or more registers, each register having two or more bits, each register configured to load data therein received in accordance with the communications protocol over the data transfer bus in a first configuration, and to load a single logic value into the plurality of bits in a second configuration. A programmable configuration register is configured to be programmed, in accordance with the communications protocol over the data transfer bus, to select two or more of the registers for loading of the single logic value into the two or more of bits of the selected registers in the second configuration.

Simultaneous control of multiple I/O banks in an I2C slave device

A system and method for synchronizing otherwise independent oscillators private to IC Bus slave devices. An IC Bus master device is capable of issuing two new general call commands, MEASURE PULSE and RESET PRESCALE. The IC Bus slave devices respond to the MEASURE PULSE command by returning a digital count related to the number of ticks its local, private oscillator cycles through during a signal pulse on the IC Bus. All such IC Bus slave devices measure the same signal pulse on the IC Bus, so the differences in the digital measurements returned during the MEASURE PULSE command are proportional to their respective oscillator frequencies. The various digital measurements returned are used to calculate appropriate oscillator prescale factors that will harmonize the final product frequencies of all of the local oscillators on all of the IC Bus slave devices in the system.

Edge-rate control circuits and methods are implemented using a variety of arrangements and methods. Using one such method, an output signal of a bus is controlled by decoupling a feedback capacitor () from a gate of a transistor () using an isolation switch (). The transistor () is used to control the output signal. A predetermined amount of charge is removed from the feedback capacitor () using a charge distribution capacitor () that is selectively coupled to the feedback capacitor () using a switch (). The switch () is enabled in response to the output signal reaching an output voltage and disabled in response to the charge distribution capacitor () reaching a reference voltage.

Method and system for a signal driver using capacitive feedback

Consistent with one example embodiment, a communications system uses an I2C serial data transfer bus that has a serial data line () and a clock line () used to implement a communications protocol. The communications system includes a slave device having address pins (), each coupled to the serial data line, clock line, power line, or ground. Communications circuitry communicates with a master device in accordance with the communications protocol over the data transfer bus. Decoding circuitry detects a first state of the address pins (), detects a second state of the address pins () subsequent to the detection of the first state, wherein one or more logic values of the address pins differ between the first state and the second state, and decodes a slave device address () as a functional relationship between the first state and the second state of the address pins.

Dynamic I2C slave device address decoder

Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate identification of inter-integrated circuit slave devices using device identification coding. The communications system includes a slave device having a device identification code identifying one or more parameters. Communications circuitry in the slave device is configured to communicate with a master device on the I2C serial data transfer bus using the communications protocol. In response to a transmission of a device identification address from the master device, the slave device is configured to transmit an ACKNOWLEDGE, and in response to a transmission of a slave device address and the device identification address from the master device, the slave device is configured to transmit the device identification code from the slave device to the master.

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Chandler, AZ, United States of America

Alma Anderson