Tower Semiconductor Ltd.

Allon Parag

Yakov Roizin

Roda Kanawati

Sharon Levin

Micha Gutman

Vladislav Dayan

Avi Parvin

Efraim Aharoni

Eran Lipp

Einat Arad Ophir

Einat Ophir Arad

Yosef Avrahamov

For example, a multi voltage-domain Electro Static Discharge (ESD) power clamp may include a plurality of pins; and an ESD array including a cascaded plurality of ESD power clamps. For example, the ESD array may include a plurality of ESD array portions configured to protect a respective plurality of voltage domains from ESD. For example, the ESD array may be configured to connect the plurality of ESD array portions between a respective plurality of pin pairs from the plurality of pins. For example, an ESD array portion corresponding to a voltage domain may include one or more ESD power clamps of the cascaded plurality of ESD power clamps. For example, the ESD array portion may be configured to protect a voltage range of the voltage domain.

Multi voltage-domain electro static discharge (ESD) power clamp

An SOI IC includes a polysilicon/silicon plug extending through the buried insulation layer between a P-type handle layer and a P-type device layer. An N-type well region is formed in the device layer over the polysilicon/silicon plug, and then a high-voltage (HV) device is formed in the well region such that part of its drift region is located over the polysilicon/silicon plug. Doping of the well region, the polysilicon/silicon plug and the handle layer is coordinated to form a P-N junction diode that couples the HV device, by way of the polysilicon/silicon plug, to a ground potential applied to the handle layer, thereby increasing the HV device's breakdown voltage by expanding its depletion region to include the handle layer. The polysilicon/silicon plug grows in holes formed through the insulation layer during the epitaxial silicon growth process used to form the device layer.

Method of forming high-voltage silicon-on-insulator device with diode connection to handle layer

A back-end metallization structure for non-volatile memory (NVM) and other semiconductor devices including low-moisture-content oxide cap layers that suppress the creation and migration of mobile hydrogen atoms/ions during back-end processing. The metallization structure includes multiple metallization layers formed over front-end e.g., polysilicon (floating gate) structures and a pre-metal dielectric layer. Each metallization layer includes a patterned metal (e.g., aluminum) structure covered by an interlevel dielectric (ILD) layer (e.g., BPSG, USG or FSG). Each cap layer is formed using a high-density low-moisture content oxide such as silane oxide (i.e., SiOgenerated by way of a silane CVD process) that is deposited over the ILD layer in lower metallization layers to serve as an etch-stop for the subsequently-formed metal layer, and to isolate the ILD material from the plasma environment during aluminum over etch, which significantly reduces the production and migration of hydrogen that diminishes charge storage by the floating gates.

Floating gate NVM with low-moisture-content oxide cap layer

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Ramat Ishai, Israel

Allon Parag