Microsoft Technology Licensing, LLC

Allison Klein

Leonardo Esteban Blanco

Silvana Patricia Moncayo

Max Alan McMullen

Michael I Borysenko

Daniel Wood

Brian T Klamik

Keith D Melmon

Michael P Crider

Craig C Peeper

Mark Stefan Grossman

Charles Neil Boyd

Amar Dinesh Patel

Matthew David Sandy

Chas Boyd

William Kristiansen

Matt Lee

In one embodiment, a graphics processing unitmay support a logical resource using a physical tile poolfor sparse data sets. The graphics processing unitmay allocate a physical memory allocation into a primary physical tile pool. The graphics processing unitmay define a mapping for a logical tile setfor a logical resource. The graphics processing unitmay selectively map a primary logical tileof the logical tile setto a primary physical tileof the primary physical tile pool

Hardware-accelerated resource tiling

Buffer display techniques are described. In one or more implementations, at least part of an off-screen buffer is rasterized by an application to generate an item for display by the computing device. One or more communications are formed that describe the part of the off-screen buffer which contains the item that is to be copied to update an onscreen buffer.

Buffer display techniques

Systems and associated methods for processing textures in a graphical processing unit (GPU) are disclosed. Textures may be managed on a per region (e.g., tile) basis, which allows efficient use of texture memory. Moreover, very large textures may be used. Techniques provide for both texture streaming, as well as sparse textures. A GPU texture unit may be used to intelligently clamp LOD based on a shader specified value. The texture unit may provide feedback to the shader to allow the shader to react conditionally based on whether clamping was used, etc. Per region (e.g., per-tile) independent mipmap stacks may be used to allow very large textures.

GPU texture tile detail control

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Seattle, WA, United States of America

Allison Klein