Agere Systems Inc.

Agere Systems Guardian Corp.

Lucent Technologies Inc.

Allen Yen

Yi Ma

Steven Alan Lytle

Stephen Ward Downey

Huili Shao

Thomas Michael Wolf

Chun-Yung Sung

William Graham Easter

Simon John Molloy

Sudhanshu Misra

Frank Miceli

John Albert Maze, Iii

Nace Layadi

Susan Clay Vitkavage

Daniel Joseph Vitkavage

Richard William Gregor

Yifeng Winston Yan

Frank Yauchee Hui

Gerald W Gibson, Jr

Paul B Murphey

Brian David Crevasse

Joseph Ashley Taylor

The invention includes a process for manufacturing an integrated circuit, comprising providing a substrate comprising a dielectric layer over a conductive material, depositing a hardmask over the dielectric layer, applying a first photoresist over the hardmask and photodefining a trench, etching the hard mask and partially etching the dielectric to form a trench having a bottom, stripping the photoresist, applying a second photoresist and photodefining a slit across the trench, selectively etching the dielectric from the bottom of the trench down to the underlying conductive material. Both the hardmask and the second photoresist are used as a mask. Later, a connection to the underlying metal is formed and integrated circuits made thereby.

Define via in dual damascene process

A monolithic integrated circuit including a capacitor structure. In one embodiment the integrated circuit includes at least first and second levels of interconnect conductor for connection to a semiconductor layer and a stack of alternating conductive and insulative layers formed in vertical alignment with respect to an underlying plane. The stack is formed between the first and second levels of conductor. Preferably the stack includes a first conductive layer, a first insulator layer formed over the first conductive layer, a second conductive layer formed over the first insulative layer, a second insulator layer formed over the second conductive layer, and a third conductive layer formed over the second insulative layer, with the first and third conductive layers commonly connected.

Stacked structure for parallel capacitors and method of fabrication

The present invention provides a semiconductor device, including an interconnect and a capacitor, and a method of fabrication therefor. The method includes forming a damascene interconnect structure through an interlevel dielectric layer and a dielectric etch stop layer located under the interlevel dielectric, wherein the damascene interconnect structure contacts a first interconnect structure. The method further includes forming a metal-oxide-metal (MOM) capacitor damascene structure through the interlevel dielectric layer and terminating on the dielectric etch stop layer. The damascene structures, may in an alternative embodiment, be dual damascene structures. Furthermore, the damascene interconnect structure and the MOM capacitor may, in another embodiment, make up part of a larger integrated circuit.

Damascene structure having a metal-oxide-metal capacitor associated therewith

Integration of low dielectric material in semiconductor circuit structures

A process ( ) for forming a metal interconnect ( ) in a semiconductor device ( ) using a photoresist layer ( ) having a thickness (T) of no more than 0.66 microns without forming a notch in the side ( ) of the interconnect. A reactive ion etching process ( ) used to remove portions of a metal layer ( ) to form the interconnect includes a burst etch step ( ) wherein a first high flow rate ( ) of passivation gas is delivered, followed by a main metal etch step ( ) wherein the flow rate of passivation gas is reduced to a second lower value.

Method for avoiding notching in a semiconductor interconnect during a metal etching step

The present invention provides a method that includes defining a dummy gate structure comprising a spin on glass on a semiconductor substrate, forming a dielectric layer over the dummy gate structure, removing the dummy gate structure to form a gate opening within the dielectric layer, and forming a gate material comprising a metal within the gate opening.

Method of forming a reverse gate structure with a spin on glass process

An integrated circuit device and method of making include an interconnect structure and a capacitor. The interconnect structure includes a metal line and a contact, and the capacitor includes upper and lower metal electrodes. The method includes forming a dielectric layer adjacent a semiconductor substrate, and simultaneously forming a first opening for the interconnect structure and a second opening for the capacitor, in the first dielectric layer. The method further includes selectively depositing a first conductive layer to fill the first opening to form the interconnect structure, and forming the upper and lower metal electrodes with a capacitor dielectric therebetween to form the capacitor in the second opening. The integrated circuit device provides a high-density capacitor having metal electrodes and which is compatible and integrated with dual damascene structures. As such, the capacitor is situated in a same level as a dual damascene interconnect structure.

Method of making dual damascene interconnect structure and metal electrode capacitor

An apparatus for determining endpoint in the chemical mechanical polishing of a metal film using an acidic slurry includes a hydrogen sensor which senses the amount of hydrogen vapor being produced as a result of the reaction between the metal film and the acidic slurry. When the concentration of hydrogen vapor in the reaction area drops, endpoint is attained and the polishing operation may be terminated or otherwise adjusted. Hydrogen sensing elements include a palladium gate MOS transistor, expandable plastics and a tungsten oxide film.

Apparatus for chemical mechanical polishing endpoint detection using a hydrogen sensor

A method for making a transistor includes the steps of providing a silicon substrate including a silicon-germanium epitaxial layer, forming a masking implant layer on a channel region of the silicon-germanium epitaxial layer, and implanting dopants into the silicon-germanium epitaxial layer using the masking implant layer to define spaced apart source and drain regions adjacent the channel region. The method further includes the step of removing the masking implant layer after the implanting to expose the channel region. A silicon epitaxial layer is formed on the exposed channel region, and at least a portion of the silicon epitaxial layer is converted to silicon oxide to define a gate dielectric layer for the transistor. The gate dielectric layer includes a gate oxide layer, and a silicon protection layer between the gate oxide layer and the channel region. A conductive gate is formed on an upper surface of the gate oxide layer. Since the gate dielectric layer does not include germanium, a stable gate dielectric layer is provided for the high speed silicon-germanium transistor.

Silicon-germanium transistor and associated methods

A method for stripping photoresist material (,) from a semiconductor substrate (,) avoids incorporation of sodium and other contaminant ions from a rework solvent. An oxygen and hydrogen plasma mixture strips the photoresist material without significant introduction of oxygen into the titanium nitride layer (,). Any oxidation of the titanium nitride is reversed by exposing the substrate to an oxygen-free, reducing plasma, such as a hydrogen-containing plasma. The titanium nitride layer is thereby much less susceptible to incorporation of contaminant ions in a subsequent cleaning with rework solvent than a layer which has been extensively oxidized during the plasma stripping process.

Process for photoresist rework to avoid sodium incorporation

The invention includes a process for the production of semiconductor devices comprising the steps of depositing a metal layer on a semiconductor substrate, depositing a hardmask layer on said metal layer, depositing a photoresist on said hardmask layer, patterning said photoresist, thereby exposing and patterning portions of said hardmask layer, etching said exposed portions of said hardmask layer with a hardmask etchant, thereby exposing and patterning portions of said metal layer, removing, or not, said photoresist, and etching said exposed portions of said metal layer with a metal etchant and semiconductor devices made by said process.

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Orlando, FL, United States of America

Allen Yen