Advanced Micro Devices Corporation

Other

Allen S Yu

Paul J Steffan

Thomas C Scholer

Patrick K Cheung

Jeffrey Allan Shields

Bharath Rangarajan

James N Pan

Chau M Ho

Ramkumar Subramanian

Allison Holbrook

Pei-Yuan Gao

Narendra Patel

For fabricating dual gate structures of complementary transistors, a gate material is deposited into an opening disposed over a P-well and an N-well having the complementary transistors formed therein. An ion species is implanted into a portion of the gate material to form a first gate structure over one of the P-well or the N-well. The gate material remains to form a second gate structure over the other one of the P-well or the N-well. A thermal anneal is performed such that the ion species and the gate material react within the first gate structure.

Fabrication of dual work-function metal gate structure for complementary field effect transistors

For fabricating dual gate structures of complementary field effect transistors, a gate material is deposited into an opening disposed over a P-well and an N-well having the complementary field effect transistors formed therein. A portion of the gate material disposed over one of the P-well or the N-well is modified to form a first gate structure, and the remaining gate material over the other one of the P-well or the N-well forms a second gate structure. The first and second gate structures form the dual gate structures of the complementary field effect transistors.

For fabricating a shallow trench isolation structure, a notched masking structure is formed over an active area of a semiconductor substrate. A shallow trench opening is formed at a side of the active area with a top corner of the shallow trench opening being exposed and facing a notched surface of the notched masking structure. Liner oxide is formed in a thermal oxidation process at the top corner of the shallow trench opening to round the top corner of the shallow trench opening. The liner oxide may also be formed on walls including the bottom corner of the shallow trench opening during the thermal oxidation process. The shallow trench opening is then filled with a trench dielectric material to form the shallow trench isolation structure.

Fabrication of shallow trench isolation structures with rounded corner and self-aligned gate

A method of manufacturing a semiconductor device having features with a dimension of &frac12;the minimum pitch wherein the minimum pitch is determined by the parameters of the manufacturing process being used to manufacture the semiconductor device. A target layer of material to be etched with dimensions of &frac12;the minimum pitch is first etched with masks having a dimension of the minimum pitch and the target layer of material is then etched with the masks offset by &frac12;the minimum pitch.

Pitch reduction using a set of offset masks

A method of manufacturing a semiconductor device with a reduced bit-line isolation dimension. After a layer of image sensitive photoresist is patterned and developed with openings having the minimum printable dimension, the layer of photoresist is silylated causing the layer of photoresist to swell, which causes the opening dimension to decrease.

Methods to form reduced dimension bit-line isolation in the manufacture of non-volatile memory devices

An ultra-large scale integrated circuit semiconductor device is provided which has inverted trapezoidal gates with LDD structures having gradual doping profiles and salicided for contacts. The structures are manufactured on a substrate by forming a barrier layer over the substrate, forming a gate layer over the barrier layer, forming inverted trapezoidal gate trenches into the gate layer that are a function of the thickness of the gate layer, depositing a gate dielectric in the inverted trapezoidal gate trenches on the substrate, forming polysilicon gates in the inverted trapezoidal gate trenches, removing the gate layer and the barrier layer to define gate spacers, implanting the substrate around the gate spacers with a dopant to form source/drain extension junctions, and preparing the source/drain extension junctions and the gates for conductive connections.

Controlled gate length and gate profile semiconductor device and manufacturing method therefor

A method of analyzing defect images in a semiconductor manufacturing process wherein descriptors are assigned to images of defects caught during scanning of an inspection wafer. The images, assigned descriptors and linkage data are stored in a relational database. An operator can select an image to analyze and the review station assigns descriptors to the selected image and the database is searched for images having the assigned descriptors.

Composition based association engine for image archival systems

Methods of manufacturing semiconductor devices having low resistance reduced channel length transistors. Spacers are formed on each side of trenches that define the location of transistor channels. The spacers are formed with a dimension between the spacers that is less than a dimension available from photolithography systems currently available. A layer of gate oxide and a polysilicon gate are formed within the dimension resulting in transistors having channels length less than that available from standard photolithographic methods of forming gates and channels.

Method of forming low resistance reduced channel length transistors

A method of reducing the effect of placement errors during defect capture and analysis during the manufacture of integrated devices on semiconductor wafers wherein defects from a current layer are evaluated in relation to defects from previous layers after an oversized overlay map has been utilized to perform a best-fit analysis of current defects and previous defects, the oversized overlay map reduced and a trend analysis performed to determine error type and the coordinates of defects translated to their proper location.

Overlay radius offset shift engine

A method of analyzing and classifying defects on a semiconductor wafer during a semiconductor manufacturing process using an automatic defect resizing tool to accurately measure the sizes of defects.

Automatic defect resizing tool

A reduced device geometry semiconductor memory device is provided which has increased device efficiency because of an increased gate coupling coefficient. Shallow trench isolations are formed in a semiconductor substrate. The shallow trench isolations are selectively shaped in order to form a control gate dielectric layer later with a large width relative to the width between the floating gates.

Semiconductor with increased gate coupling coefficient

Ultra-large scale CMOS integrated circuit semiconductor devices are provided which have width- and profile-controlled, inverted trapezoidal gates with LDD structures having gradual doping profiles and salicided for contacts. The structures are manufactured on a substrate by forming a barrier layer over the substrate, forming a gate layer over the barrier layer, forming inverted trapezoidal gate trenches into the gate layer, depositing a gate dielectric in the inverted trapezoidal gate trenches on the substrate, forming polysilicon gates in the inverted trapezoidal gate trenches, removing the gate layer and the barrier layer to define gate spacers, implanting the substrate around the gate spacers with a dopant to form source/drain extension junctions, and preparing the source/drain extension junctions and the gates for conductive connections.

Controlled gate length and gate profile semiconductor device

A scan tool recipe management database system for recipes utilized in the scanning of semiconductor wafers during the manufacture of the semiconductor wafers. The scan tool recipe management database system includes workstations at each scan tool for simultaneously inputting recipes and changes to the recipes to the scan tool and to a scan tool recipe database.

Recipe management database system

A wafer having a substrate and an insulating layer over the substrate that includes a conductive layer over the insulating layer. The conductive layer mitigates charges formed on a photoresist layer during etching of features (e.g., vias and trenches). Any conductive material may serve this purpose. For example, aluminum, tantalum nitride, titanium and titanium nitride. Typically, a plasma etcher is employed for forming vias and trenches in an insulating layer to create contacts and conducting lines used to connect devices residing within different layers. The plasma etcher causes charge buildup on a photoresist layer that is utilized during the etching process. The charge buildup causes potential differences on the photoresist layer, which can lead to eventual damage of devices. A conductive layer eliminates this potential differences because a charge equilibrium is established due to the conductivity of the conductive layer.

Reduction of via etch charging damage through the use of a conducting hard mask

A method of inspecting a semiconductor wafer using scanning tools to find defects that occur during the manufacturing process and to the automatic classification, automatic selection of defects that require further analysis, the automatic selection of the equipment to perform the further analysis and the in-situ performance of the further analysis that includes destructive and non-destructive analysis.

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Fremont, CA, United States of America

Allen S Yu