Agilent Technologies, Inc.

Keysight Technologies, Inc.

Hewlett-packard Company

Allen Montijo

Steven D Draving

Michael Thomas McTigue

Matthew S Holcomb

David J Dascher

Christopher P Duff

Scott Allan Genther

Joseph D Shaker

Connor P McKay

Vivian Patlin

Marty Grove

Martin B Grove

Caleb Remington Begly

David Poppe

A method for applying digital signal processor (DSP) blocks in a configurable order includes providing a plurality of DSP blocks for performing a plurality of different signal processing operations on input data. The method further includes providing a sorting switch for connecting the DSP blocks together in a configurable order to implement a signal processing task. The method further includes configuring the sorting switch to apply the DSP blocks in a predetermined order to implement the signal processing task. The method further includes switching input data from the sorting switch to the DSP blocks in the predetermined order to implement the signal processing task.

Methods, systems, and computer readable media for applying digital signal processor (DSP) blocks in configurable sequences using sorting switch

A system and method are provided for displaying input signals from a DUT on a display screen. The method includes sending a data stream of digitized data received from the DUT to an FPGA for serial decoding; receiving decoded symbols from the FPGA; identifying valid symbols among the decoded symbols indicating transitions between the decoded symbols; storing the valid symbols with corresponding time-tags as valid packets in memory, and discarding ones of the decoded symbols occurring between the valid symbols; and plotting on the display screen the valid packets occurring between beginning and ending valid packets of the stored valid packets. The beginning valid packet has a corresponding time-tag occurring immediately before a first point time-tag associated with a left edge of the display screen, and the ending valid packet has a corresponding time-tag occurring at or immediately before a last point time-tag associated with a right edge of the display screen.

System and method for performing lossless compressed serial decoding

A measurement system is provided that has a digital edge trigger circuit that is capable of operating at the full signal bandwidth of the measurement system. The digital edge trigger circuit comprises a plurality of processors that process time-interleaved digital data samples output from respective time-interleaved ADCs to perform edge trigger detection. The processors share edge detection information with one another to increase the speed at which edge trigger detection is performed to enable the digital edge trigger circuit to operate at the full signal bandwidth of the measurement system.

Measurement system having a digital edge trigger detection circuit that is capable of operating at the full signal bandwidth of the measurement system

A measurement system is provided that performs a trigger data acquisition algorithm. When the measurement system performs the trigger event data acquisition algorithm, it causes a preselected number of digital data samples acquired during a first time window that includes a trigger event and during a second time window that is specified by the user and that is subsequent in time to the first time window to be stored in memory. Digital data samples acquired after the end of the first time window and before the beginning of the second time window are not stored in memory. By not storing digital data samples acquired after the end of the first time window and before the beginning of the second time window, the possibility of overwriting samples that surround the trigger event is prevented and the memory is used very efficiently.

Measurement system that stores samples acquired during a time window that includes a trigger event and during a subsequent user-specified time window

A measurement system is provided that performs a qualified store algorithm. When performing the algorithm, the measurement system stores in memory digital data samples acquired during a time window while a qualification signal is valid, a preselected number of digital data samples acquired prior to and adjacent in time to the time window, and a preselected number of digital data samples acquired subsequent to and adjacent in time to the time window.

Measurement system that stores pre- and post-qualification signal data

An apparatus and method for determining if ringing in an output signal from a receiver that processes an input signal is the result of a bandwidth limitation in the receiver that processes an input signal rather than ringing in the input signal is disclosed. The apparatus includes the receiver and a ring suppression filter. The ring suppression filter receives the receiver output signal and generates a ring suppressed output signal therefrom. The receiver and the ring suppression filter provide a first aggregate system response such that the ring suppressed output signal does not include ringing introduced by the receiver. The first aggregate system response is linear in phase.

Filter for identifying signal artifacts in bandwidth-limited instruments

Equalized Acquisition Record are prepared from Original Acquisition Records reflecting Total Jitter and from an existing description of DDJ. Removal of timing DDJ alters the locations of edges associated with data events. Voltage DDJ adjusts the asserted voltage in the central portion of a Unit Interval. One technique for equalizing timing jitter variably interpolates along the existing Original Acquisition Record to discover plausible new voltage values to assign to existing sample locations along the time axis. Another technique construes the desired amount of correction for each data event as an impulse that is applied to a Finite Impulse Response Filter whose output is a Voltage Correction Waveform having a smoothed voltage excursion. Time variant voltage values output from the Finite Impulse Response Filter are collected into a Voltage Correction Waveform Record having entry times found in the Original Acquisition Record. An entry by entry addition of these two Records produces the Equalized Acquisition Record.

Method for equalizing a digital signal through removal of data dependent jitter

Separation and analysis of measured Total Jitter (TJ) begins with a suitably long arbitrary digital test pattern, from which an Acquisition Record is made. A Time Interval Error (TIE) or Voltage Level Error (VLE) Record is made of the Acquisition Record. A Template defines a collection of associated bit value or transitions that are nearby or otherwise related to a bit location of interest, and has associated therewith a collection of Descriptors and their respective Metrics. Each Descriptor identifies one of the various different patterns of bit value or transitions that fit the Template. The TIE/VLE Record is examined, and a parameter is measured for each instance of each Descriptor for the Template. The collection of measured parameters for each particular Descriptor are combined (e.g., averaging) to produce the Metric for that Descriptor. A Look-Up Table (LUT) addressed by the different possible Descriptors is loaded with the associated discovered Metric, which is a plausible value for Data Dependent Jitter (DDJ) at that bit. DDJ separates from TJ because DDJ is correlated with the Descriptors, while Periodic Jitter (PJ) and Random Jitter (RJ) can be expected to average to near zero over a sufficient number of instances of a given Descriptor. Identified instances of DDJ are individually removed from corresponding locations of TJ found for the entire waveform (the original TIE/VLE Record) to leave an Adjusted TIE/VLE Record that is PJ convolved with RJ.

Method of finding data dependent timing and voltage jitter for different bits in an arbitrary digital signal in accordance with selected surrounding bits

Measurement of jitter in a system uses a digital test sequence including many repetitions of a test pattern. An Acquisition Record is made of the entire test sequence. A complete Time Interval Error (TIE) Record is made of the Acquisition Record. The complete TIE Record is separated into a collection of Component TIE Records, one for each transition in the test pattern, and that collectively contain all the different instances in the test sequence of that transition in the test pattern. An FFT is performed on each component TIE Record, and the component FFTs are processed to obtain timing jitter data for the digital signal.

Method and apparatus using re-sampled tie records to characterize jitter in a digital signal

Discovery of RJ assumes an Adjusted TIE Record for TJ from which DDJ has been removed. What remains is PJ+RJ, from whose Fourier Transform PJ is 'synthetically de-convolved' to leave just RJ: Calculate the Power Density Spectrum of PJ+RJ, and determine a threshold that indicates a PJ component. Identify in the PDS the largest frequency component that exceeds the threshold, otherwise there is no significant PJ and PJ+RJ can be taken as RJ. If a frequency component exceeds the threshold, take the largest and calculate what the convolution of it with the FT of the Transition Pattern would be if this circumstance were to occur in isolation, and then remove it from PJ+RJ. Repeat with continued iterations, until there are no further PJ components.

Finding random jitter in an arbitrary non-repeating data signal

Discovery of DDJ within measured Total Jitter (TJ) begins with a suitably long digital Test Pattern, from which an Acquisition Record is made. A Time Interval Error/Voltage Error Record is made of the Acquisition Record. A Template defines a collection of associated bit value or transitions that are nearby or otherwise related to a bit location of interest, and through the applied test pattern produces a sequence of Data Symbols. The TIE/VLE Record is examined, and a parameter is measured for each Data Symbol as it occurs in the Test Pattern. A regression technique may be use to find coefficients for a DDJ Calculator whose inputs are the Data Symbols and whose output is respective values of DDJ. Subsequent separation of DDJ from TJ is possible because DDJ is correlated with the Data Symbols, while Periodic Jitter (PJ) and Random Jitter (RJ) can be expected to average to near zero over a sufficient number of instances of a given Data Symbol.

Finding data dependent jitter with a DDJ calculator configured by regression

A method of data acquisition for a digital instrument having a bandwidth. The method includes receiving a signal and associated trigger. Using that trigger, a plurality of signal values is sampled at multiple time intervals to create an acquisition record representing a continuous fractional segment of the signal. The plurality of samples meets the Nyquist requirement for the bandwidth but is in error according to at least one known error mechanism. The acquisition record is then processed with DSP techniques to produce a compensated acquisition record corrected for the at least one known error mechanism. Each associated compensated acquisition record is incorporated into a result acquisition record as a segment thereof corresponding to a continuous fractional segment of the signal whose signal values were sampled in an associated instance. An additional signal and additional associated trigger are received. The above steps are then repeated for the additional signal and additional associated trigger.

Method for digitally acquiring and compensating signals

Trial decimations are performed on an acquired waveform. Each trial produces a sequence of packets applied to a complexity detection circuit. Each packet contains a decimation value to be used in place of acquisition values to be suppressed along a decimation sample width. Each packet also includes the maximum and minimum values that occurred within the associated decimation sample. A plurality of counters record for a trial decimation the number of instances when the differences in waveform extremes exceed a corresponding plurality of selected thresholds. Complexity introduced by decimation will tend to produce waveforms having larger voltage excursions over the region of suppressed acquisition samples. The data in the counters is processed to produce a suite of histograms examined to select a decimation factor that does not introduce significant additional complexity.

Waveform complexity detector

A measurement system for analyzing data values that are stored in memory and that represent a sampled electrical signal under analysis (SUA). Each of the data values represents the SUA at respective points in time over a time interval during which the SUA was sampled. The stored data values constitute a main data record. The system includes processing logic that is configured to generate at least a first reduced data record from the main data record. The first reduced data record comprises a subset of the data values of the main data record. The first reduced data record is processed by the processing logic to locate an edge (i.e., a voltage transition) in the first reduced data record. Thus, it is not necessary that the main data record, which is more voluminous than the first reduced data record, be used to locate the edge. After the edge has been located, the processing logic processes a second set of data values of the main data record that is within boundaries in the main data record associated with the first reduced data set in order to analyze the edge. Thus, it is not necessary to process the entire main data record in order to analyze, or evaluate, an edge. Once the edge has been suitable located, all of the data of the main data record that is associated with the edge may be processed to analyze the edge.

Measurement system for sampling a signal and evaluating data representing the signal

Sampling techniques and circuits for a waveform measuring instrument. The sampling techniques and circuits process a series of digital signal samples through a set of sample extractors and subsequently process the extracted digital signal samples. The set of sample extractors include a uniform decimator, a low frequency dither decimator, and a digital peak detector. The uniform decimator extracts a uniform decimated sample value for each decimated sample interval in a series of decimated sample intervals. The low frequency dither decimator extracts a low frequency dither decimated (random) sample value for each decimated sample interval in a series of decimated sample intervals. The digital peak detector extracts a maximum sample value and a minimum sample value for each decimated sample interval in the series of decimated sample intervals. The subsequent processing of the samples includes selecting samples from the set of extracted samples, storing the selected samples, retrieving the selected samples, potentially manipulating the selected samples mathematically or analytically interpreting the selected samples, and displaying the manipulated or analyzed sample values.

Growing community of inventors

Colorado Springs, CO, United States of America

Allen Montijo