At&t Bell Laboratories

Bell Telephone Laboratories

American Telephone and Telegraph, Co.

At&t Information Systems Inc.

Allen L Larson

Scott E Farleigh

John S Helton

Gary J Grimes

Hung-San Chen

Frank C Liu

A structure for providing an N by N optical switch includes input and output structures disposed on either side of a planar electronic shutter array. Each of the input and output structures, which respectively provide optical signal splitting and combining, is realized by the stacking of N molded optical elements. Each element is formed of a plurality of molded materials with one providing an optical waveguide and the other providing a supporting structure for such waveguides. Advantageously, both the input and output structures utilize the same molded optical element and are fabricated in an identical manner. After such fabrication, the one structure to be designated as the output structure is rotated 90 degrees with respect to the input structure prior to abutment against the planar electronic shutter array.

Optical switch incorporating molded optical waveguide elements

A broadband ISDN communication system (10) comprises a plurality of bit-serial synchronous time-division multiplexed ring networks (15) interconnected by a circuit switch (11). In each network, terminal equipment (14) is interfaced to a fiber-optic ring bus (12) by add/drop multiplexers (13). Single time slots (201) on the ring function as independently-assignable channels. Each time slot carries one bit at an 8 Kbps rate. Ring bandwidth is 45 Mbps. The circuit switch is a time-division multiplexed time-space switch. The time stage (301) comprises a plurality of time slot interchangers (TSI 303), one for each switch output port (306). Each TSI unit is connected to all switch input ports (305) and through the space stage to its corresponding output port. The space stage (302) is a time-multiplexed space stage. The switch is fully non-blocking and has broadcast capability. System bandwidth is dynamically allocated to users in single time slot (8 Kbps) increments, under control of a network manager (16).

Broadband multirate switching architecture

The subject wideband switching network provides inexpensive point-to-point wideband communication connections. Wideband source and destination terminal equipment are either connected to modems which encode the analog signals used by the wideband source terminal equipment into digital signals for transmission through the wideband switching network and decode the received digital signals into analog signals used by the wideband destination terminal equipment; or are directly connected to the wideband switching network if source and destination terminal equipment transmit and receive digital signals. The modems are connected to the wideband switching network by optical fibers. The wideband switching network is a point-to-point space division switch that is comprised of a matrix of high frequency semiconductor crosspoints. Wideband communication connections are originated by a subscriber transmitting connection control signals to the wideband switching network controller on a dial-up basis from a telephone station set, on a data link from a computer or directly from a keyboard associated with the wideband switching network controller. The wideband switching network can concurrently switch any combination of voice, audio, video, data.

Wideband switching system

The subject channel interface circuit functions in a multiprocessor environment to provide a high speed interface between a processor and the communication channel which interconnects all the processors. The communication channel carries data messages, which messages contain a header field specifying source, destination and control information. The subject channel interface circuit is programmable and serves to dynamically translate the header portion of the data message as it is received and thereby determine whether this data message is to be stored in the processor memory. If the data message is to be stored, the channel interface circuit immediately converts the header field into a hardware address, which is used to activate a specific location in processor memory. The data message is then inputted (via DMA) to this memory location and the appropriate buffer pointers are reset. Thus, the subject channel interface circuit performs all the data receiving tasks, including message storage and linking, without requiring the involvement of the associated processor.

Channel interface circuit with high speed data message header field

The subject channel interface circuit functions to provide a high speed interface between a processor and a data link, which link carries data messages having virtual addresses. The message handler is programmable and serves to translate the header portion of the data message from a virtual address into a hardware memory address, which is used to activate a specific location in the processor memory. The data portion of the data message is then directly inputted to this memory location (i.e., DMA) and the appropriate file pointers are reset. When a complete file is received and stored in memory, the message handler generates a processor interrupt. Thus, the subject message handler performs all the data receiving tasks, including file storage and linking, without requiring the involvement of the associated processor. All known prior art message handler circuits require extensive processor involvement in the data storage operation and thereby significantly reduce the effective data transfer capabilities of the link.

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Thornton, CO, United States of America

Allen L Larson