At&t Bell Laboratories

Allen L Gorin

Richard Robert Shively

Patrick A Makofsky

Stephen E Levinson

Christopher A Stanziola

Umberto F Gianola

Robert N Lewine

Neal C Oliver

Nancy Morton

A machine-based learning system receives inputs and proposes outputs using a network of connection weights to relate the inputs to the outputs. When a user affirms a proposed output, the system adjusts the connection weights to strengthen the relationship between elements of the inputs and that output. Learning occurs in the course of successive iterations as the connection weights adapt to relationships between semantically-significant input elements and related outputs. The system can be used to acquire language from inputs provided in the form of text or speech such that the connection weights adapt to semantically-significant words without need for defining word meanings. Such language acquisition contrasts with previous systems in which words are predefined.

Machine-based learning system

An interconnection scheme among the processing elements ('PEs') of a multiprocessor computing architecture realizes, through PE reconfiguration, both fault tolerance and a wide variety of different processing topologies including binary trees and linear systolic arrays. By using a novel variant on a tree expansion scheme, the invention also allows for arbitrary up-sizing of the PE count to build virtually any size of tree network, with each size exhibiting same high degree of fault tolerance and reconfigurability. The invention may be practiced with 4-port PEs arrayed in a module comprising a 4.times.4 board-mounted PE lattice. Each PE has four physical ports, which connect to the similar ports of its lattice neighbors. Each PE has an internal capability to be configured to route signals to or from any of its neighbors. Thus, for tree topologies, any of the four neighbors of a given PE may be selected as the parent of the given PE; and any or all of the remaining three neighboring PEs may be selected as the child(ren) PEs. The PE ports are configured under the control of a remote host, which establishes an initial desired PE topology. The operability of the PEs is tested, and information on faulty PEs or communications paths is used to enable or disable nodes as necessary by revising the PE port configurations. The nodes thus are reorganized and can run or continue running, on a degraded basis.

Reconfigurable signal processor

The present multiprocessor computing architecture uses a Host device to communicate directly with each processor of an array. The processors are identical, but initially unindividuated. Each is capable of generating on command an identification indicia, expressable as a number. Using the set of such numbers, the Host executes an interactive initialization protocol, through which each processor assumes a digitially coded address or label related to its generated number. The label thereafter is used by the Host to transmit data or to order data from the so-identified element. One Host-processor configuration uses direct broadcast for communications and, therefore, is not reliant on conventional physical, that is hard-wired, paths. Need to place individual processors in particular locations with respect to one another, or in a predetermined configuration such as a tree, is obviated.

Associated memory computer with floating non-wired cells

A binary tree multiprocessing array of plural signal processing elements, and having input/output for the array entirely through a root one of the processing elements, includes in each processing element thereof a hardware, pipelined, floating point, multiply/accumulate processing function for cooperating with a procesing element memory and a processing element input/output processing function to perform signal pattern matching of input digital signal sequences provided to and/or through the root processing element with respect to at least one digital signal sequence pattern stored in the memory.

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Fairlawn, NJ, United States of America

Allen L Gorin